A few days later, Apple CEO Steve Jobs was demonstrating what the combination of an accelerometer and three-axis gyroscope could do in a mobile handset. ST made its own video for the company’s Field Trip, a series of presentations to financial analysts, to show how the gyro and accelerometer combination could be used to navigate through the streets of Venice - using dead reckoning where the signals from GPS satellites cannot be easily seen in narrow streets.

As ST is the only vendor claiming to make an integrated three-axis gyroscope, this is the one that is suspected to be inside the iPhone 4. Teardown experts such as Chipworks and TechInsights believe die markings confirm ST as the manufacturer.

Benedetto Vigna, head of ST’s MEMS division, claimed that the market for gyros in consumer will be three times bigger than that for similar sensors in automotive – where they are more widely used today for stabilisation control – by 2014.

Although the initial demonstrations revolve around games, Vigna said dead-reckoning calculations can make it possible to pinpoint a user’s location inside buildings such as shops and museums, narrowing location-based information to a rack of clothes or a museum exhibit.

Although it does not need all three axes, optical image stabilisation is another use for cameras and phones. Papa said applications for the MEMS gyro can go further, including vibration control in washing machines. “The potential market is huge,” he said.

According to Benedetto Vigna, the decision to make a three-axis gyro was taken quite late in the day in an indication of how integration and fast turnaround are becoming crucial in getting MEMS into high-volume consumer designs. “By the end of last year, we understood that the market was willing to move faster,” said, explaining that the company had been working on a two-axis design.

“On the 21st October, we put the first transistors on the layout. And you are now holding the product,” he said as he handed out tiny 4x4mm packages. “Because of the nimbleness of the team we now have a three-axis gyroscope.”

The rationale from Aart de Geus, CEO of Synopsys, in the conference call for the purchase is not all that different from Cadence’s. “Putting together these IP blocks and making sure they work together is essential,” he said.

Like Cadence, Synopsys is expecting an increase in the use of third-party IP by chipmakers. “The trend of IP outsourcing is a massive trend. People are moving towards using commercial IP where they can except where they can add differentiation,” de Geus said, adding that a growing number of companies are realising what they thought was differentiated home-grown IP could be just a millstone. “What companies produce is not necessarily differentiated. Some of the standards they need to work with are so complex, their own people can’t necessarily do a cost-efficient job there. The downturn has helped many executives realise that outsourcing these efforts makes a lot of sense.”

De Geus argued that very little of the IP produced by Virage overlaps with that created at Synopsys. The EDA company backed away from the acquisition of memory-IP specialist Mosys in 2004 and has not developed its own. Even earlier, a move into standard-cell IP through the acquisition of Silicon Architects in the mid-1990s ended when Synopsys wound up the operation. De Geus explained that the move was “premature” and that it had gone into the business before it had a place-and-route tool (later acquired through its 2002 purchase of Avant) that would make use of those cells.

Virage’s roots lie in low-level IP such as memory cores and standard cells but has, more recently, moved into larger cores through the acquisition of ARC International and NXP Semiconductors’ IP design group. Potentially, the addition of the Virage line-up brings Synopsys into conflict with ARM, with which Synopsys developed the verification reuse and low-power design methodologies.

De Geus argued that the processors from ARC complement those of ARM, agreeing with one analyst’s use of the term ‘ancillary’ to describe them. “ARM is one of our most important partners and is a friend of the company, a company around which we have built a number of our offerings. ARC is interesting because it so supports the ARM core processor. It provides a controller that can be used for subtasks to offload the main processor. It will be interesting to see how we can build solutions with ARM.”

ARM has gradually backed away from areas that Synopsys has moved into in the IP space. The ARM Primexsys portfolio of peripherals failed to take off but Synopsys’s main successes in IP lie in this area. Although ARM has tried to get into digital signal processing (DSP), it is another area that the UK company has discontinued its effort, choosing to focus on graphics instead. ARC has, in contrast, focused heavily on audio and similar DSP-based products.

Where ARM and Synopsys will compete head-on is in standard-cell libraries and it’s a business where ARM has spent heavily to keep up with process technology. Having Virage provides Synopsys with a way to align design-implementation tools with the cell libraries, something that is becoming more important as design rules get ever more restrictive. Will ARM engineers get the same access to the Synopsys tools people post-acquisition?

“In 1997, we saw the first terascale machines. A few years ago, petascale appeared. We will hit exascale in around 2018,” said Wilfried Verachtert, high-performance computing project manager at IMEC, explaining that these machines will be able to perform 10¹⁸ floating-point calculations per second.

The most powerful supercomputer being made today is the Cray XT5 Jaguar with a rated performance of close to 2 petaflops

At a presentation held to celebrate the opening of a new cleanroom at IMEC and the foundation of the ExaScience lab, Martin Curley, senior principal engineer and director of Intel Labs Europe, said: “We are focused on creating the future of supercomputing. We have a job to do of creating a sustainable future. Exascale computing can really change our world.”

Curley said a the two main problems will be power consumption and the difficulty of writing highly parallel software. The performance required is the equivalent of 50 million laptops which would demand thousands of megawatts of power.

He explained that, by the time exascale computers are likely to appear, silicon-chip geometries will have dropped to 10nm. Although these devices can potentially run at tens of gigahertz, Curley said power consumption concerns would force supercomputer makers to run them much more slowly and potentially even slower than today’s processors. The move will demand billions of processing units in one supercomputer. “How are we going to achieve that? The only way is through billion-operation parallelism.”

Curley added: “Even with just 10 to 12 cores, we see the performance of commercial microprocessors begin to degrade. The biggest single challenge is parallelism.”

The ExaScience lab will, as its test application, work on software to predict the damage caused by the powerful magnetic fields that follow solar flares in the hope of providing more accurate information to satellite operators and the power-grid companies.

With current-generation supercomputers, the mesh used to analyse field strength has elements that are a million kilometres across, far larger than the Earth itself. An exascale machine would make it possible to scale the mesh size down to elements that are 10,000km across.

Verachtert said the project aims to get the power consumption of a machine from 7000MW – based on today’s technology - to 50MW, “and that is still higher than we want”.

One problem with a supercomputer than contains millions of discrete processors, each one containing thousands of processing elements, is the expected failure rate. “My optimistic projection is that there will be a failure every minute. It’s possible that there will be a failure every second. We have to do something about that.”

The failure rate will have a knock-on effect on programming. Today, it is possible to break up applications so that portions can be re-run after a hardware failure, which may happen once a day. That is impossible as the size of the machine scales up. Verachtert said the methods programmers use will have to take account of processors failing, using checkpoints and other techniques such as transactional memory – which Intel has researched heavily already – to allow code to be re-run automatically without disrupting other parts of the application.

Set up by ARM and a bunch of chipmakers, Linaro is different to some of the others that have appeared over the past few years, which are mainly intended to provide ready-made environments for mobile phones and internet tablets.

All of these groups run the risk of being home to nothing more than tumbleweed. A bundle of source code gets dumped in shortly after creation but interest wanes as developers concentrate on the major platforms - right now that’s likely to be Android.

At first sight, Linaro does not look too interesting to developers working with Android and its analogues. But that probably won’t affect Linaro’s success because this group scratches an itch that the chipmakers themselves have, which is the massive cost of developing low-level software for their applications processors. Since the late 1990s, as I describe in this feature for Engineering & Technology, the chipmakers have been bundling more and more software with their devices. But they haven’t picked up any more cash for their efforts.

Instead of doing all the work individually, and spend loads of money, they can club together. Most of them are ARM-based and they have broadly similar system architectures, although things such as the graphics accelerators will differ substantially. Amortising the cost of the support software for environments such as Android and WebOS is not going to solve the chipmakers’ software problems overnight - there are other platforms they need to support - but more cooperation at this level can put a dent in the heavy cost of development.

ARM has already kicked off a similar endeavour for its Cortex-M microcontrollers, although it operates differently to the open-source consortia. The Cortex Microcontroller Software Interface Standard (CMSIS) is designed to support a library of functions that users can bolt into their embedded controllers and has the backing of Cortex-M licensees such as NXP Semiconductor and STMicroelectronics. You can view Linaro as an extension of that kind of effort but with a different target: the Cortex-A series and mobile terminals.

It will be interesting to see if other independent developers turn up and contribute but that may not matter as these are companies with a ton of developers now who have customers who want to base their systems around at least one of the higher-level Linux platforms.

Although the company expects to increase the amount of production that it outsources to foundry from its current level of 15 per cent to 20 per cent long-term, ST decided recently to put more investment into Crolles in a bid to quickly move to parity with the processes supplied by the major foundries and to be able to build its own derivative processes, such as the recently announced 32LPH process which uses a high-k metal-gate transistor structure.

Jean-Marc Chery, CTO of ST told analysts at the company’s annual Field Trip: “I am confident we will be able to to tape out in our 20nm low-power process the first product by Q4, 2012. This will gain more 30 per cent performance and a 2x shrink factor [over the previous process technology].”

Chery said the company is prototyping with its 32nm process and expects delivery of its first production immersion scanner next week so that production can ramp up in the third quarter of next year. This process ramp will follow just one quarter after the ramp for its low-power 40nm process. The 45nm process will ramp up in the fourth quarter of this year.

Although all this expansion might look like a one-way bet in the current market conditions, where you can pretty much sell everything you can make, by the time all of this capacity is meant to come onstream it could well be a different story.

Already trying to fill the second phase of its fab in Dresden as fast as possible with chipmaking gear, GlobalFoundries said at the Computex trade show in Taipei that it will build another section - once grants from Germany turn up - over the next two years. This will add 20,000 wafers per month, increasing Dresden’s capacity by one-third when that expansion has finished. Given that they have not started building the extension yet, this is a very aggressive schedule for filling a fab.

However, the schedule for the Malta, New York fab has slipped slightly. Originally slated to go into volume production in 2012, this is now not expected to happen until 2013. By the end of 2012, it will just be pilot production. However, Malta does not miss out on the capacity splurge. Fab 8’s peak capacity moves up from 42,000 wafers per month to 60,000 - eventually. Based on previous estimates from GlobalFoundries, this is unlikely to happen before the end of 2015.

Pushing the volume ramp at Malta back a bit may, if current market projections prove correct from analysts such as Future Horizons and IC Insights, help GlobalFoundries avoid walking straight into a capacity glut in 2012, and still capitalise on a recovery in 2013. However, things rarely work out that neatly in this business.

There’s more. GlobalFoundries’ owner ATIC said it would build a 3km² ‘technology cluster’ in its home of Abu Dhabi. There is no firm news of a fab being built there other than strong hints: “GlobalFoundries is committed to partnering with ATIC to share best practices and expertise in cluster creation in the near-term and putting a significant technology and manufacturing presence in the region long-term.”

Let’s have a look at the rationale. Design costs keep going up - in proportion to the number of gates you can squeeze onto an integrated circuit (IC).

“The only thing that scales is IP. You can’t move to the stratosphere in terms of abstraction. You have to use IP…The SoC battle is won or lost over the quality of IP…IP reuse will go up to and beyond 90 per cent of the die. But having multiple IP vendors for one chip design brings challenges, so you will qualify IP vendors rather than individual IP cores. Everything points to consolidation.”

Oh no, wait. That wasn’t Cadence. Those were the words of Raul Camposano in mid-2004, who was then Synopsys CTO. Sounds a lot like the Cadence rationale doesn’t it? But it doesn’t say a lot for Cadence’s new found strategy rewriting the rules of EDA. It’s easy to see how an EDA-plus-IP strategy can develop because you only have to look at what has happened at Synopsys, the only major EDA vendor so far to have made a living at IP. Mentor Graphics had a go but that did not turn out so well and the company got out of the business.

Since the Internet bubble, the share of Synopsys’s revenues from IP has hovered around 6 to 8 per cent according to a succession of 10K annual-report filings. The share was as high as 10 per cent in 2001 but this was before the company acquired Avant, when the IP share slid to 5 per cent.

Synopsys’s 2003 revenues totalled $1.2bn. In 2009, they came to $1.4bn. IP revenues averaged about 7 per cent of the total in 2003, providing Synopsys with $84m just before Camposano made his prediction about the rise of IP. Now, they amount to $140m. That’s about 9 per cent per year, about the same as the semiconductor industry’s long-term average growth. It’s not transformative growth by any means. This wasn’t because Camposano was wrong - far from it - just that the increased use of IP does not necessarily translate into massive sales.

As chip capacity increases - which pulls in more third-party IP - design starts go down, slowing down the growth of the IP suppliers. You could argue that maybe Cadence has entered the market at just the right time. But it takes time to establish a reputation as a stable, reliable IP supplier as Synopsys chairman and CEO Aart de Geus pointed out in the company’s most recent results conference call. Buying Denali gives Cadence greater credibility in the market than simply bootstrapping its own operation but it will take time for the company to see a return on its $300m, if it sticks at it.

The German company decided to go to the US International Trade Commission in February, claiming that Elpida had infringed some of its patents. As Infineon backed out of the memory business with the closure of Qimonda, it looked as though the German chipmaker aimed to claw back some cash by finding infringers of memory-related patents. It has wound up with a patent cross-licence which, although is not to be sniffed at, doesn’t sound like a wholesale victory.

To get the money rather than the cross-licence from patenting it’s important not to be actually making stuff (and so it’s just as well that most semiconductor patents are in the hands of companies making stuff otherwise the whole industry would grind to a halt).

Back in the late 1990s, as startups rushed to get chips into the market and cash out with an initial public offering (IPO), the Tality subsidiary seemed to Cadence a good way to get more money out of the design business. Tality was to be a ‘design factory’ for chips. You came in with an idea, Tality - for a fee - provided you with the chip design that you could then get fabbed at a foundry.

There was only one problem: Tality lost money on the deal. It could never charge enough to cover its costs and, eventually, the whole operation was wound up or sold off in bits.

One part of the Tality plan was to develop commonly used blocks of IP and use it across different projects, with the advantage that the engineers knew how to tie it together. Fast-forward ten years and you have a broadly new management team in at Cadence trying to work out how it expand its business without having to commit to the expensive R&D needed for deep sub-micron chip-design tools.

Having realised that making lumps of IP work together is not often straightforward, the team came up with the idea of doing a lot of that integration work for the customer. Other than the name, it sounds as though a part of Tality rides again.

As it will take at least a year to build the shell, Fab 15 - which was originally earmarked for Tainan rather than its revised location of Taichung, roughly midway between TSMC HQ in Hsinchu and Tainan, before the chip market imploded in 2001 - will not play much of a role in TSMC’s production before 2012.

When it gets going, chairman and CEO Morris Chang, said Fab 15 will support capacity expansion for the 40nm process and will add 28nm before moving onto the 20nm technology and beyond.

In the meantime, TSMC is rushing to get more equipment into Fab 12 and Fab 14, pushing 300mm production up by 35 per cent by the end of the year. However, Chang said these fabs are nearing their planned maximum capacity of 100 000 wafers per month. The company plans to use the majority of its capital expenditure for 2010 in the first half of the year to ensure much of the extra capacity is in place by the end of 2010.

Older 200mm fabs are not to be left out of the expansion - Shanghai, in particular will see new equipment for the “more than Moore” programme the company adopted to keep its older fabs running.

TSMC saw a modest rise in sales from the fourth quarter of last year to the first quarter of 2010 rather than the expected post-Christmas dip.

CFO Lora Ho said: “Contrary to expectations, first quarter revenues and wafer shipments slightly increased.” The growth was driven by communications and consumer products, coupled with stronger demand on the recently introduced 40nm process, helped by improving yields.

Chang said yields on the 40nm are now as good or better than those encountered on the previous 65nm process at the same stage of its development. In the first quarter, the foundry sold $411m worth of wafers to customers made using the 40nm process – revenues from the 65nm process passed the $400m point two years ago.

“Combined revenue from 40nm and 65nm processes accounted for 41 per cent of total wafer sales,” said Ho.

Numonyx has pushed the write endurance of 128Mbit phase-change memory (PCM) devices to the point where it is now ten times that of typical flash memories and has launched a family of parts to replace DRAM and flash in embedded systems. The company is now working on higher-capacity memories to go into future cellphone designs, agreeing to use the same interface as competitor Samsung.

Giuseppe Crisenza, vice president of strategic alliances for Numonyx, said the company has been optimising the technology on a 90nm process since it launched the first memories in late 2008. In that time, the write endurance increased from 100,000 to 1 million cycles.

Because flash memories have lower cycle counts they need to use techniques such as wear levelling to prevent overused bits rendering the devices useless. PCM devices have the further advantage of allowing individual bits to be written unlike flash memories that have to be erased in blocks and rewritten.

Numonyx will sell both serial- and parallel-interface versions of the 128Mbit PCM, aiming mainly at the general embedded market rather than the mobile-phone business, although Crisenza said there are low-end mobile phones for the Asian market that could use the devices.

“There are a lot of applications that for cost reasons prefer the serial interface,” said Crisenza.

Even in displays, some companies are now looking at a way to cut the cost of making existing types of screen, such as liquid-crystal display (LCDs) rather than trying to open up a market for organic LED screens, especially now that Sony has retired hurt - although Peter Harrop, chairman of IDTechEx, the company that organises the conference, reckons they will be back with updated versions at some stage.

Sharp is seriously looking at a way of using printing to replace lithography in the manufacture of its LCDs. According to Tolis Voutsas, director of the materials and devices applications lab at Sharp Laboratories of America, the company could knock 60 per cent out of the cost of making some LCDs simply by “abolishing lithography”, once printed transistors get to the necessary level of performance.

This will be the third round of the Taiwanese foundry’s attempt to demonstrate that it is ahead of the process curve compared even to Intel, which went into volume production with a 32nm process at the end of last year. However, as with TSMC’s 28nm and 40nm processes, it’s hard to know how this will compare to the 32nm and 45nm nodes that appear on more conventional roadmaps. With games like these, it’s easy to see why the International Technology Roadmap for Semiconductors (ITRS) gave up on the idea of naming nodes. Instead, it focuses on actual on-silicon measurements in its estimates of when processes will become available.

Based on what TSMC presented at conferences in recent years, the 40nm process has measurements such as contacted gate pitch - the key one for transistor density - which were consistent with Intel’s more conventional nomenclature. One library supplier pointed out that TSMC’s 40nm process was pretty much its 45nm process but with more restricted design rules.

Until IEDM rolls round at the back end of this year, TSMC is unlikely to publicly disclose the reality of its ‘20nm’ process, although big customers will know what they’re dealing long before that.

What will be a plus point for TSMC, although it sounds a little strange, is that the company will almost certainly be enforcing highly restricted design rules in the 20nm process - but this will be the third iteration of that move. Because of its use of a gate-last manufacturing process at 28nm, similar to the approach used by Intel since 45nm, TSMC already needs to make sure designers use a small selection of shapes in their standard-cell libraries. Gate-last manufacturing tends to provides opportunities for strain engineering but with the downside of being less tolerant to design variation.

As there is no plan to move to extreme ultraviolet and the technique of source-mask optimisation is also on the table - in which the shape of the light beam is tuned to the on-chip structures used on the finest geometry layers - it is going to be straight lines all around as far as chip design is concerned. But much more of the infrastructure for designing that way will be in place by 2011/2012 (as initial production is meant to start at the end of 2012).

TSMC is confident that anyone using gate-first right now will have to switch to doing it the other way real soon now even if their customers have had a bit more freedom in the design department. I guess TSMC sees it as an advantage in saying they have ‘leapfrogged’ the competition in measurements even though it’s the same kind of trick the other camp can do. They have already done the trick of launching a 28nm half node hot on the heels of the originally planned 32nm version of the process. There is plenty of time for Common Platform foundries to turn up and say: “Oh look what we’ve found, a 20nm process.” They might as well call their processes Turbo and Super for all the good this grade inflation does. People doing chip design will have other metrics they are worried about.

“We are putting in place a vision that ensures SSMC is in a good position for the next decade or two,” said CEO Jagadish CV.

Jointly owned by NXP Semiconductor and Taiwanese foundry TSMC, SSMC was one the last big 200mm digital logic-oriented fabs to be constructed, opening just ahead of the dot-com crash. It produced the first yielding silicon in October 2000, so barely turned in a quarter’s worth of production wafers before the slump.

After the recovery, 300mm production with 0.13µm copper processes had pretty much taken over from 200mm, which because of the decisions made by production-equipment makers, were stuck on 0.15µm and larger linewidths and aluminium metal interconnect.

Rather than throw in the towel, SSMC changed direction, concentrating on ‘ABCD’ products — analogue, bipolar, CMOS and DMOS. Basically, stuff that wasn’t the standard CMOS turned out by 300mm fabs owned by TSMC and others.

It took $3m, according to Førre, to get the Gecko out of the door and employ, as of October, around 30 people. The remainder was seen as enough to get the company to the middle of this year and has since taken on some more people, taking its headcount to 35. To get further, the company has raised $13m in venture funding. Last year, Førre said Energy Micro was looking for around $10m, arguing that it need not take much to get a fabless startup off the ground and into revenue.

Talking about the initial funding needed for the company, Førre noted: “People say: ‘That’s outrageous. You need far more money to bring up a semiconductor company’. I say: ‘yes, we can do that’.”

Førre said the company spent around $3m to get the EFM32 to market and had “just south of” 30 staff working at its launch. That figure has now risen to 35. The device is built using TSMC’s 0.18µm ultralow-leakage (180ULL) process.

“In reality, even though we are working on very aggressive process technology, mask cost is a small fraction of the money you are burning. The cost is primarily the labour,” Førre said, adding that the company went straight to a full mask, without pursuing the cheaper multiproject wafer option first.

“All of the digital functionality was tested out on FPGA and we used extensive mixed-signal simulation. If you tell people you are designing for a test chip, they will work to that,” said Førre, so he was keen to ensure that the first chip produced at fab should be the real product.

According to Førre, Chipcon spent around $9m before it turned in a profit and was ultimately bought by Texas Instruments.