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TSMC pulled a switcheroo at the International Electron Device Meeting (IEDM) in a further piece of technology oneupmanship following on from its claim of an early move to 28nm earlier in the autumn.

Director of advanced process development Carlos Diaz was scheduled to talk about the company's 32nm high-k, metal-gate process - one that does not actually appear on TSMC's official roadmap now that 28nm has supposedly taken over. The official proceedings are all about the 32nm process. But when Diaz took to the stage, it was a different story: he was there to describe what the company had done with its 28nm process.

This time, there was to be no confusion similar to what happened with the 45nm process where, by the time TSMC launched it commercially, it had transmuted into a 40nm. This 28nm process has different measurements.

Now, is it really a 28nm process? It depends on how you look at it. I think Kaizad Mistry of Intel was right last year when he said contacted gate pitch is the critical measurement that determines how dense a process can be. And density is the reason why people move to more advanced processes. But, you could also argue that SRAM cell size is just as important, especially now that most chips have big banks of the memory on-chip.

If you look at contacted gate pitch, then what TSMC calls a 28nm process would be a 32nm process at Intel. Diaz reported a pitch of 117nm at IEDM on Wednesday. Intel's late paper on its 32nm process came in with a figure of 112.5nm.

Intel, however, has been more conservative with the SRAM cell the company proposed. However, there is a fair amount of latitude in this metric as there is a clear trade-off between size and noise. The smaller they get, the more noise you see in the SRAM circuits. Too much noise and the circuits begin to fail. TSMC pushed to get a cell that measures 0.13µm². Intel was happy with 0.17µm²

It was a similar story last year in the duel over 45nm, where TSMC showed a smaller SRAM cell but its gate pitch was not as tight as Intel's. This time around, TSMC wants to demonstrate that it has a disinct 28nm process but there is still a question mark over whether this 28nm is not simply a tight 32nm.

Researchers at MIT have developed a way to draw lines on wafers that are just 25nm across and spaced 25nm apart much more cheaply than today's fancy immersion lithographic steppers. The bad news is that the $2m tool developed by Mark Schattenburg, Ralf Heilmann and two graduate students at MIT can only do parallel lines right now. But the technique could provide an alternative way of doing double patterning that could potentially push optical lithography well into the next decade.

The technique, which is based on the 'nanoruler' developed a few years back, uses interference patterns generated by pumping 100MHz sound waves into a crystal through which they shine a laser beam. Heilmann said: "We use a transducer to change the properties of the sound wave at a very fast rate. We have updates rates of 10kHz or so. Changing the sound wave changes slightly the phase of the light wave that goes through the crystal."

By recombining the light split from a laser under the control of vibrating crystals, it is possible to create very fine interference patterns. These produce extremely thin lines on the wafer. The researchers worked with a laser operating at a wavelength more than 50 per cent longer than the 193nm deep-UV light used by today's steppers. But the interference pattern leads to sub-30nm lines. But they are quite widely spaced: about 200nm apart.

To get the line density up, the team used four passes. This takes time but Heilmann said the process can be applied across a wafer rather than being limited to a 600mm² reticle.

In its current form, the scanning-beam interference lithography can only make parallel lines. “We are working on changing the optical design to do a greater variety of patterns,” said Heilmann.

Although the technique might be used to create just regular structures, one possibility is that interference lithography might be combined with conventional lithography. For starters, companies such as Intel have already started to use more regular structures. In this approach, long lines could be patterned across the surface of the wafer and then cut into gates, for example, using an existing stepper. Very often, silicon transistor gates are way, way wider than they are long. And this pattern-and-cut trick is an approach that Intel already uses with conventional steppers on the 45nm Penryn devices.

One issue for the future is that of line-edge roughness. This roughness is becoming more and more of a headache because it increases the variability of transistors. Just cutting that variability in SRAM transistors, which tend to be more densely packed than others on a typical chip design, could pay off in better yield.

"Line-edge roughness is not a limiting factor but it is close to being one," said Heilmann.

Schattenburg said in the release: "There are several new technologies on the horizon that have the potential for alleviating these problems. These results demonstrate that there's still a lot of room left for scale shrinkage in optical lithography."

It's taken more than 35 years to find, but it looks as though HP Labs has found a cousin to the resistor and the capacitor hiding in the delicate thin films of metal oxides.

Naturally, HP Labs talks up the prospects of the memristor. One application the researchers have put forward is as a potential successor to devices such as the venerable DRAM. On the face of it, this is arguably the worst place to go. The industry is littered with 'nearly there' memories that have better properties than those apparently on offer with the memresistive approach. The HP labs team namechecks a bunch of materials in the Nature paper that show memresistive-like effects. However, at least three major categories are already in production or have multiple teams working on them, with varying degrees of success.

Chalcogenides are the materials that go into phase-change memories of the kind being pushed by Numonyx - the JV formed by Intel and STMicroelectronics. To give you an idea of how long it can take to get a memory technology off the ground, phase-change memories have been around about as long as Leon Chua's theory of the memristor. And you still can't buy one in the shops. On top of that, the phase-change memory is meant to be non-volatile: it doesn't forget stuff when you take out the battery.

The memristor will not be a non-volatile memory but only semi-non-volatile, according to the researchers. It seems that, like a capacitor, these things 'leak' a little. Leave it too long, and it will have forgotten what you told it.

This is a problem that afflicts the latest new memory technology: metal oxide, which is also being touted as a possible candidate for the memristor treatment. Metal-oxide memories are programmed by heating. Unfortunately, right now, just storing them at room temperature provides enough energy after a few days, or even hours, for them to reset themselves.

Then you have the perovskites, such as barium titanate. These are already in use in ferroelectric memories. You can go out and buy these but it's another memory technology that never quite made it to the mainstream.

However, it seems that something like memristor behaviour has been seen in organic materials. This may be the way forward as it points to the possibility of being able to print memory devices using organic chemicals. These kinds of material make pretty rubbishy transistors, but they might perform better as memristors.

The part that might lead to radical changes in computer design is the observation that memristors work in a similar way to the Hodgkin-Huxley model of the neuron.

One big problem with nanoscale electronics is variability: these things are so small that there's way too much of it. This makes it tough to build reliable binary switches: the primary use of a conventional transistor. But, what if you don't want to make a switch? This is the kind of work being performed by researchers such as Professor Steve Furber's group at the University of Manchester with the EPSRC-funded Spinnaker project. The idea behind the project is that you dump binary logic in favour of a system that lies on statistics. In that kind of environment, manufacturing variability is not necessarily your friend, but it's way less of an enemy.

The inspiration for the work is the brain and the way that neurons communicate with each other. In Prof Furber's model, you use a bunch of them together to effectively vote on a calculation. The overall elements wind up bigger but you use the elements to process more information than just binary bits. Right now, the team is using arrays of ARM processors to model neurons. However, if the work pays off, it might point to a simplified system that could be implemented using either nanonscale transistors or elements such as memristors, which have the advantage of working more like a neuron out of the box, as it were.