According to the story, Infineon chairman Max Dietrich Kley thinks buying NXP Semiconductor, currently owned by private-equity KKR, is a good idea. Chief executive Wolfgang Ziebart disagrees strongly. There is no real way to reconcile these differences so one of them will have to go, and it will probably be Ziebart. As the story in FTD sums up:

Despite Ziebart's competence, "in a shark-tank like Infineon he is out of place," said a senior manager.

Naturally, HP Labs talks up the prospects of the memristor. One application the researchers have put forward is as a potential successor to devices such as the venerable DRAM. On the face of it, this is arguably the worst place to go. The industry is littered with 'nearly there' memories that have better properties than those apparently on offer with the memresistive approach. The HP labs team namechecks a bunch of materials in the Nature paper that show memresistive-like effects. However, at least three major categories are already in production or have multiple teams working on them, with varying degrees of success.

Chalcogenides are the materials that go into phase-change memories of the kind being pushed by Numonyx - the JV formed by Intel and STMicroelectronics. To give you an idea of how long it can take to get a memory technology off the ground, phase-change memories have been around about as long as Leon Chua's theory of the memristor. And you still can't buy one in the shops. On top of that, the phase-change memory is meant to be non-volatile: it doesn't forget stuff when you take out the battery.

The memristor will not be a non-volatile memory but only semi-non-volatile, according to the researchers. It seems that, like a capacitor, these things 'leak' a little. Leave it too long, and it will have forgotten what you told it.

This is a problem that afflicts the latest new memory technology: metal oxide, which is also being touted as a possible candidate for the memristor treatment. Metal-oxide memories are programmed by heating. Unfortunately, right now, just storing them at room temperature provides enough energy after a few days, or even hours, for them to reset themselves.

Then you have the perovskites, such as barium titanate. These are already in use in ferroelectric memories. You can go out and buy these but it's another memory technology that never quite made it to the mainstream.

However, it seems that something like memristor behaviour has been seen in organic materials. This may be the way forward as it points to the possibility of being able to print memory devices using organic chemicals. These kinds of material make pretty rubbishy transistors, but they might perform better as memristors.

The part that might lead to radical changes in computer design is the observation that memristors work in a similar way to the Hodgkin-Huxley model of the neuron.

One big problem with nanoscale electronics is variability: these things are so small that there's way too much of it. This makes it tough to build reliable binary switches: the primary use of a conventional transistor. But, what if you don't want to make a switch? This is the kind of work being performed by researchers such as Professor Steve Furber's group at the University of Manchester with the EPSRC-funded Spinnaker project. The idea behind the project is that you dump binary logic in favour of a system that lies on statistics. In that kind of environment, manufacturing variability is not necessarily your friend, but it's way less of an enemy.

The inspiration for the work is the brain and the way that neurons communicate with each other. In Prof Furber's model, you use a bunch of them together to effectively vote on a calculation. The overall elements wind up bigger but you use the elements to process more information than just binary bits. Right now, the team is using arrays of ARM processors to model neurons. However, if the work pays off, it might point to a simplified system that could be implemented using either nanonscale transistors or elements such as memristors, which have the advantage of working more like a neuron out of the box, as it were.

Discarding the possibility that Apple has decided the move to Intel, and its rejection of PA's PowerPC processor in 2006, has been an awful mistake and it suddenly needs to press the architecture reset button, the move by Apple suggests that the company is not all that happy with the shape of today's integrated circuit (IC) business.

One possibility is that Apple has decided it needs more in-house chip designers and buying PA was a quick way to staff up. That's not unusual in this business: it's a surprisingly common way of getting hold of people who can design the analogue circuits that most electronics engineers fear to touch. Even after you've bought in a bunch of processors and memory, there are other places a computer maker can use experienced IC designers to get an edge on its competitors. You don't see that much in the PC business but it's a lot more common in places like the phone market.

Historically, Altera and market leader Xilinx have taken lumps out of each other as they vied to be first onto each manufacturing process. But something changed at the 65nm process node. Xilinx was quick to get its high-end parts out on the 65nm technology, but nowhere near as quick as the company's claims over having first silicon on that process. Altera was behind but took the opposite tack: putting its cheaper Cyclones onto TSMC's 65nm process first. Then it all went quiet. The launch of the 45nm process went off with both Altera and Xilinx being uncharacteristically quiet. It began to look as though a kind of chip that had become the foundries' banker for early silicon had suddenly fallen off Moore's Law.

It seems that the programmable-logic makers are still in the running, just not as quick to jump on a new process as they used to be. And it seems that Altera wasn't aware just how advanced its next process would be until TSMC decided it would lop another 5nm off - in name at least.

Basically, Blaze and TSMC have cut a deal that will see the Taiwanese foundry use a version of the Blaze MO tool to alter transistors in a layout to make them less leaky just prior to manufacturing. The idea is not new and fairly simple: you make the transistor gate longer on logic paths that don't need to be fast. This typically shifts the threshold voltage up, which cuts leakage. STMicroelectronics has been offering the same sort of modifications using different logic cells. What is different is the nature of the deal between Blaze and TSMC and what it could mean for the whole DFM business.

Instead of trying to sell tools on a per-seat basis for something like a couple of hundred thousand dollars – the regular EDA business model – TSMC will host the tool. Although the companies will not talk about the money side of the deal, it does look broadly similar to the Artisan free-library model, where the foundry paid a royalty to Artisan for each chip made and charged a bit more for each chip to the customer.

For Jacob Jacobsson, CEO of Blaze DFM, this approach, in a way, opens up money that isn't available to the EDA tools vendors. "EDA has a had a more or less stagnant $3bn budget for as long as we can remember. It is more attractive for us to align with the manufacturing side of the business."

With the 32nm generation, IBM and its partners expect to be able to deliver a process that exceeds the industry consensus on what is needed at that point. The consensus is summed up in the pile of documents that go by the name of the International Technology Roadmap for Semiconductors (ITRS). Taken together, the documents are effectively the guidelines for what the industry needs to stay on Moore's Law.

Scattered throughout the PDFs are tables of specifications that semiconductors should get close to if they are to be useful at a given process geometry. The numbers are all colour coded: yellow means tricky but possible; red means nobody has an answer yet, or at least one they've shared in public.

Other than that, the content of today's missive is not broadly different from the one that IBM and its partners put out just ahead of the chipmaking industry's big conference on process technologies, the International Electron Device Meeting in Washington DC, held late last year. There really isn't a lot more detail, other than there is now a timetable: IBM will start running prototypes for customers of the companies in its Common Platform alliance in the third quarter of this year. The implication is that the company's in the Common Platform team will have a working 32nm process in the second half of 2009, about the same time as Intel and TSMC as long as they stay on schedule.

That ST sees it as a purchase was made clear in the second conference call that ST held after the call it hosted jointly with NXP's Frans van Houten. On the first call, where everybody was really happy to be working together, van Houten wanted to point out that the Dutch-American chipmaker was in NewCo for the long haul, albeit with a 20 per cent share of the new company. That combination of option calls described in the release was just a formalisation of a possible exit, just in case.

Carlo Ferro, chief financial officer of ST, made the position much clearer on the second, NXP-less call. "It is evident that ST starts with a 80 per cent and has identified a possible opportunity for a further move. ST has granted a call option after three years and NXP has a put option. The future exit cost will significantly depend on the future financial performance of the company."

Now here's the important bit: "ST is prepared for any possible evolution but we exclude the possibility to separate the business [from ST]. And we are prepared through the exit formula to consolidate the business."

Later on, Ferro added, when talking about the effect of the options on ST's financial performance, which he claimed should more or less cancel each other out on the balance sheet: "It is an opportunity to eventually buy the business at predefined terms."

I was sitting at the Many-core and Reconfigurable Supercomputing (MRSC) conference in Belfast the other week wondering the same thing. In recent years, hardware-specific EDA has been a dirty word. Mentor Graphics, which made its name selling proprietary workstations before it became a software-only company made a foray back into hardware in a deal with Mercury Computer Systems in late 2006. Mercury used the IBM Cell processor – the same one used in the Sony Playstation 3 – to speed up the job of checking chip designs before they go to fab. Mercury sells the hardware and Mentor provides a special version of Calibre.

It's not clear how well hardware acceleration has gone for Mentor and Mercury. However, in its 2007 annual report, Mercury declared that it saw a "slight rebound" in its semiconductor business, partly due to the sale of one accelerator for chip-mask inspection – which is not related to Calibre – and its deal with Mentor. The number-three EDA company has been busy showing off the hardware at events like the SPIE lithography conference, so the company must have some faith in the idea of speciality accelerators.

Maybe IBM does. But it's not alone. What IBM claimed in the press release was that a memory 100 times denser than today's flash devices is on its way:

"The devices would not only store vastly more information in the same space, but also require much less power and generate much less heat, and be practically unbreakable; the result: massive amounts of personal storage that could run on a single battery for weeks at a time and last for decades."

Sounds great. When can I buy one? Not any time soon if you look more closely at what IBM's release is based on. The journal Science has published a paper on the work of Stuart Parkin's group at its Almaden lab in San Jose that describes a tweak to a type of magnetic memory. It's a bit like a solid-state disk state. You store bits magnetically: the state depends on which way the stored field points, either forwards or backwards along a metal wire.

The argument used for the merger is not all that dissimilar to Borel's: it's all about scale. Borel wanted Infineon, NXP and ST to team up to be big enough to build and operate a leading-edge fab - it is something that is only worth doing if you are selling billions of dollars' worth of chips every year out of that facility. Not able to do that on their own, the three companies expect to buy wafers made using the latest processors from foundries such as TSMC.

The availability of foundry-made silicon is one reason why Infineon chief Wolfgang Ziebart has said that there is not all that much point in trying to be big for the sake of being able to keep building fabs. His view is that companies will specialise and do whatever they can to be in the top three of their chosen market. Infineon has been bulking up in wireless recently, thanks to its purchase of a business unit that was only briefly part of LSI when that company bought Agere Systems.

The move by NXP and ST is on a larger scale, creating an as-yet unnamed joint venture that is comfortably in the top-three wireless silicon makers and around twice as big as the next largest supplier. According to iSuppli, that will be Infineon once the deal is done. The German company is at the head of a line of $500m to $1bn suppliers. The ranking switches a little if you look at it from the perspective of baseband processors - the single most important segment in cellular wireless silicon. ST lies at number three, NXP at five.

The curious thing about Silverthorne is that it is just a processor – in a market where everything it will compete with will be a system-on-chip (SoC). OK, SoC is a bit of a misnomer in the context of a portable computer as you still need a stack of chips around the main one to make anything usable. The iPhone, for example, has them stacked and squeezed together to get everything it needs into a phone-sized package. However, Intel is looking at markets where devices such as Texas Instruments' Omap rule.

It is doubly curious when you consider Silverthorne's die size: 25mm² is tiny. It is a little less than a quarter the size of the dual-processor Penryn, which clocks in at 107mm². For a desktop Intel processor, the Penryn is surprisingly small. Intel has been known to go double that size for the first iteration of a processor.

To make use of tens or hundreds of cores, you need applications that are "embarrasingly parallel". But Flautner is not so sure such things exist. His rule? That there is no such thing as an algorithm that is embarrassingly parallel, just an algorithm that hasn't been optimised enough yet. He pointed to situations in graphics where operations that used to be parcelled up and split across many processors in a dumb way have been replaced by approaches that apply more local intelligence but which are much tougher to parallelise.

I can think of one or two algorithms that remain embarrassingly parallel - they just aren't that useful. Anyone roving an electronics show in the late 1980s will remember people trying to push the Inmos transputer. If they weren't displaying scenes of shiny balls rendered by ray-tracing, they were processing the good-old Mandelbrot set.

People found lots of other ways to render scenes since then that don't parallelise so well. It's hard to think of a smarter way to generate Mandelbrot set images than the way they were processed then. But why would you want to?

The processors have already entered production: reverse-engineering specialist Chipworks is etching away the top of its sample right now to see what lies underneath. So the 45nm generation is underway. And, based on the combination of metal gates and 45nm, Intel looks to be way out in front. But it's not necessarily the case. Foundry TSMC has started running customer wafers through its most advanced fab. We can expect the chips from those wafers to go on sale soon. Matsushita has already got manufacturing runs of its Uniphier chip.

Where Intel does seem to be going it alone is on metal gates. So, it should come as no surprise that the company is focusing attention on that part of the process. However, metal gates are not necessary for making 45nm devices, only those that are likely to burn a lot of power, such as PC processors. For those operating in the low-power segments, the metal gate is something of a luxury. And it's a luxury that a lot chipmakers are avoiding, at least for this generation. Only IBM has said it will use them and it has yet to show off any chips made on a 45nm process.

Although the combination of metal and a dielectric with a higher dielectric constant than silicon dioxide stops current flowing out of the transistor out through the supposedly insulating gate, that form of leakage is only one small part of the overall power loss. In a high-speed chip such as a PC processor, most of the leakage is down to the transistor passing electricity even when it is supposedly turned off. These days, transistors don't so much switch between on and off; they go from on to less-on. As a result, most of the changes needed to deal with leakage have to happen during the design phase. And, those changes cut gate leakage as much as the other, more bothersome form: subthreshold leakage.

So, other chipmakers do not share Intel's enthusiasm for metal gates. They don't want the extra cost of shipping in sophisticated and slow equipment that lovingly deposits the novel high-k dielectric one atomic layer at a time. Even Intel may not choose to use metal gates on the products it plans for the consumer-electronics market.

TSMC last year said it was developing a metal-gate process for 45nm but, as the process got nearer to production, found that a more conventional gate structure was all that it needed. The foundry is looking at the metal gate option seriously for the 32nm process and will, if a customer really wants it, think about putting a metal gate on the existing 45nm process. But they are really going to have to want it.

However, Intel's move won't shove up the cost of making Penryns that much, it seems. In comparison with previous desktop processors, the die is pretty small. The penny you see sitting on a wafer full of Penryns in the publicity shots gives a very good idea of how small the chip is. That means Intel can get a lot more onto a wafer, reducing its overall production cost. This, most likely, more than offsets the increase in cost caused by the use of the more complex metal-gate process. And it gives Intel a potentially strong lead in any price war that it might conduct with AMD to push the advantage it currently holds. There are other companies with 45nm devices, but AMD is not one of them.