Economics: March 2010 Archives

geir-førre.jpgGeir Førre, founder and CEO of low-power microcontroller startup Energy Micro was in no hurry to raise venture funding for his company. Having sold his previous startup Chipcon to Texas Instruments, he was able to use his own money to get Energy Micro off the ground for around. And with some money from the Norwegian government and lead customers, the company had $6m to get to its first product launch, the EFM32 Gecko that appeared last year.

It took $3m, according to Førre, to get the Gecko out of the door and employ, as of October, around 30 people. The remainder was seen as enough to get the company to the middle of this year and has since taken on some more people, taking its headcount to 35. To get further, the company has raised $13m in venture funding. Last year, Førre said Energy Micro was looking for around $10m, arguing that it need not take much to get a fabless startup off the ground and into revenue.

Talking about the initial funding needed for the company, Førre noted: “People say: ‘That’s outrageous. You need far more money to bring up a semiconductor company’. I say: ‘yes, we can do that’.”

Førre said the company spent around $3m to get the EFM32 to market and had “just south of” 30 staff working at its launch. That figure has now risen to 35. The device is built using TSMC’s 0.18µm ultralow-leakage (180ULL) process.

“In reality, even though we are working on very aggressive process technology, mask cost is a small fraction of the money you are burning. The cost is primarily the labour,” Førre said, adding that the company went straight to a full mask, without pursuing the cheaper multiproject wafer option first.

“All of the digital functionality was tested out on FPGA and we used extensive mixed-signal simulation. If you tell people you are designing for a test chip, they will work to that,” said Førre, so he was keen to ensure that the first chip produced at fab should be the real product.

According to Førre, Chipcon spent around $9m before it turned in a profit and was ultimately bought by Texas Instruments.

chip-profit.jpgIndustry analyst firm iSuppli has run the numbers on companies in the semiconductor business and found they are turning in levels of operating profitability not seen since the glory days of the Internet boom.

Overall operating profitability rose to 21.4 per cent according to iSuppli in the fourth quarter of 2009, the highest level since the last quarter of 2000. Those working around the industry then will remember those heady days, which were quickly followed by a sudden post-Christmas hangover when purchasing managers staggered into their warehouses and wondered: “Cripes. Did we really order all this stuff?”

For those thinking that the world was only just beginning to move out of recession late last year, a lot of the recovery in profitability in chipmaking has come from very aggressive supply management, also known as not spending anything on stuff to make chips with. Major customers are now in the unusual position of not being able to name their price and it’s not going to get any easier for them any time soon even though the big chipmakers are now opening up their wallets to expand production capacity.

wafers-price.jpgEven during the disastrous first quarter of 2009, prices did not fall as far as they used to — because the chipmakers did not allow inventory to build up in the way it did in 1995 or 2000. In fact, prices went up for a while before falling slightly as the recovery got under. This is very different to what happened in 2001 when prices went down and kept going down. The revenue per wafer (red line) and wafer output (grey area) chart here from SICAS and SIA numbers shows what happened.

President and CEO of iSuppli Derek Lidow also cited the increasing focus of chipmakers: “The semiconductor industry has almost completely eschewed the broad-line model that once was the hallmark of the largest players in the business. Instead, chipmakers now are concentrating on specific market segments, allowing them to focus on areas where they have pricing power and a competitive advantage. This has allowed them to improve profit margins and to cut overhead.”

That position echoes former Infineon president Wolfgang Ziebart at Electronica in 2006: “Before, size was very important. This is over.”

At the same panel session, Professor Hermann Simon of Simon-Kucher and Partners went a bit further by chiding the chip industry for being “stupid” by chasing market share, and constantly dumping price to get it.

Infineon’s board thanked Ziebart for his insight by firing him and then wound up shutting down Qimonda just months ahead of a pricing recovery that might have helped the German memory maker find a buyer as a going concern rather than a source of cheap production tools for Texas Instruments.

The numbers for the second half of the last decade don’t really bear out Lidow’s assertion. Profitability fell to a lower sustained level from 2006 onward and really only took off after fab managers decided the best way to cope with the worldwide financial crisis of late 2008 was to turn a lot of machinery off. However, looking into the future, vanishing sockets and increasing focus should demonstrate what Lidow describes in the medium to long term.

At the TSMC 2010 Executive Forum, Yoji Hino from Fujitsu talked about the company's move to a fab-lite operation with the shift to 28nm. Although the Japanese company has its own fabs able to turn out 40nm devices, it will use TSMC for 28nm production.

One issue that Hino covered was the impact that the I/O ring has on device scaling from 40nm to 28nm. Unless you stuff the device full of transistors the I/O ring on wirebond devices can quickly dominate the cost because the pads don't scale anywhere near as fast as SRAM cells and logic gates. Analogue also generally doesn't benefit that much from scaling, except in terms of switching speed.

Hino presented a chart that showed good scaling from 65nm to 40nm for a device with 20 million gates of logic and 15Mbit of SRAM plus some analogue. On a 65nm process, this measures 10.1mm on a side. On a 40nm process, the dimensions reduce to 7.3mm on a side, a reduction of 48 per cent. However, the increasing dominance of the I/O ring and the analogue means that the 28nm device sees a slightly smaller reduction in area: 41 per cent for a chip that is 5.6mm on a side.

To stop the I/O ring from being too much of a burden, Fujitsu and Toshiba are cutting the pad pitch from 25µm to 22.5µm for staggered pins. The single-row pitch will drop from 40µm to 35µm. As smaller devices on 40nm could benefit from a reduction in I/O pitch, the older process will, apparently, also have the smaller staggered-pin dimensions from the end of the year, when 28nm is supposed to go live. The single-row pitch on 40nm will remain unchanged, presumably on the assumption that if a device is only using a single row of pins around the edge, it's hardly going to be pad-limited.