At the company’s executive forum held in Yokohama, Japan, TSMC’s senior vice president of R&D, Shang-yi Chiang, provided some background on why yield problems surfaced on the 40nm process — and also some indications that 28nm will not exactly be plain sailing.
Chiang pointed to the shift to immersion lithography — a choice that Intel delayed by a generation — and the use of a new low-k dielectric in the metal layers as the main culprits for the foundry’s problems. He claimed that defect density has reduced significantly since the middle of last year, when chairman Morris Chang decided to expand the team working on 40nm at TSMC.
Chiang said the move from 90nm to 65nm was comparatively simple and the relative cost quite low. “Moving to 45 and 40nm is a lot more challenging,” he said. “This is the first time we began to use 193nm immersion [lithography]. This means the photoresist during exposure is submerged in water and [presents] a very high potential defect [density].”
The low-k dielectric, with a dielectric constant 2.5, was also more fragile than its predecessor. It seems that 40nm was a partial rerun of the 130nm introduction when chipmakers discovered that soft dielectrics and packaging machinery are not the best of mates — the pressure needed to seal the package crushed the metal interconnect.