If you don't like stuff about obscure standards in system-level modelling, look away now.
A round-robin email from Simon Davidmann of Imperas and the self-styled Open Virtual Platforms (OVP) group arrived earlier today saying they have added support for version 2.0 of the Transaction Level Modelling standard (TLM), published by the Open SystemC Initiative (OSCI). No, I'm not proud of myself for getting three obscure acronyms into the one sentence.
OVP launched onto the scene just as the work on TLM2 was drawing to a close. The idea behind both is to build fast simulations of hardware designs so that you can debug them. Not only that, you can debug software programs that run on top of that hardware. It's taken since 1994 to get to the point where the electronics industry, or at least the chip-design part, accepts this is a viable way of designing hardware, but it is happening.
Imperas claimed OVP could be much faster than TLM2 and, although it was not meant to be a complete replacement for TLM2, the emphasis within their camp was that you would, for the most part, not need OSCI's stuff. The people behind OVP have, apparently, realised that this was not a viable position and have now decided to add "native TLM2 support to OVP".
If you want to get an OVP processor model that has TLM2 interfaces, you can drop a line to the people at OVPWorld. The OVP claim is that you can get hundreds of MIPS out of their models. As most processor models are written in C and then given a TLM2 interface, I've never been clear why OVP's approach should work out any faster but the system architects out there can try it out.
There is a forum at the OVP website, so I imagine you will be able to ask questions about the OVP-TLM2 interface stuff there.