Design: November 2008 Archives

If you don't like stuff about obscure standards in system-level modelling, look away now.

A round-robin email from Simon Davidmann of Imperas and the self-styled Open Virtual Platforms (OVP) group arrived earlier today saying they have added support for version 2.0 of the Transaction Level Modelling standard (TLM), published by the Open SystemC Initiative (OSCI). No, I'm not proud of myself for getting three obscure acronyms into the one sentence.

OVP launched onto the scene just as the work on TLM2 was drawing to a close. The idea behind both is to build fast simulations of hardware designs so that you can debug them. Not only that, you can debug software programs that run on top of that hardware. It's taken since 1994 to get to the point where the electronics industry, or at least the chip-design part, accepts this is a viable way of designing hardware, but it is happening.

Imperas claimed OVP could be much faster than TLM2 and, although it was not meant to be a complete replacement for TLM2, the emphasis within their camp was that you would, for the most part, not need OSCI's stuff. The people behind OVP have, apparently, realised that this was not a viable position and have now decided to add "native TLM2 support to OVP".

If you want to get an OVP processor model that has TLM2 interfaces, you can drop a line to the people at OVPWorld. The OVP claim is that you can get hundreds of MIPS out of their models. As most processor models are written in C and then given a TLM2 interface, I've never been clear why OVP's approach should work out any faster but the system architects out there can try it out.

There is a forum at the OVP website, so I imagine you will be able to ask questions about the OVP-TLM2 interface stuff there.

Yesterday afternoon, Cadence Design Systems said it plans to cut 12 per cent of its workforce - around 600 positions - and cancel deals with its consultants and contractors. Although the press release and 8K announcing the moves talks of focusing on particular areas, early indications are that the cuts have affected a broad swathe of departments.

The timing of the cutbacks suggests that this, unfortunately, is the first of two or more waves of job losses. As I understand it, this week is the last opportunity for Cadence to make the cuts and see the results fall in its final quarter of 2008. The company said it would complete the restructuring in the second half of 2009. It may be that later rounds will see certain groups being closed or sold off.

"In creating the restructuring plan, we emphasised those market segments where Cadence enjoys a leadership position, such as mixed-signal design, advanced verification and low-power design," Charlie Huang, who is acting as co-CEO for the moment, said in the statement.

The suggestion is that the era of the do-it-all Cadence has passed - the company will now step away from areas where it has failed to build up more than a minority position. The question is how deeply the company will ultimately cut. It's hard to see DFT and DFM remaining. What happens to PCB where the company has a solid if not remarkable share but has lost momentum? IC layout is not mentioned by name but that probably falls into what Huang referred to as low-power design.

Although these moves are clearly bad for a workforce that has seen its leaders stumble from one mess to another, there is a silver lining. If Cadence is not going to do it all, it signals a possible end to the suicidal all-you-can-eat deals its former management forged. If EDA companies go back to competing on the best tool for the job, it's probably the best way they can start to bring back the financial value they lost over the past few years.

I was talking to a Mentor executive yesterday before I heard that the layoffs had been announced and argued that EDA companies will probably stop issuing press releases about mega-deals with customers because the analysts will come to regard them as warning signs rather than good news.