Design: June 2008 Archives

Veteran EDA analyst Gary Smith has published an analysis of the market share that Cadentor could expect to commmand if the attempted hostile takeover of Mentor Graphics by Cadence Design Systems goes through. And he's helpfully provided a big bag of market-share percentages for the important slices of the two businesses.

I disagree with Gary's representation of hardware emulation being equivalent to ESL verification, but that's really more a matter of terminology in the context of an analysis of Cadentor's position. The biggest competitor to the EDA vendors in the ESL verification space is the home-brew lash-up, which is no criticism of the home-brew approach. Since the 1990s, when I saw Matlab being combined with FPGA prototype boards and other simulation tools by one design consultancy, I have seen some very elegant approaches to ESL verification.

However, I can also accept that there are two types of ESL verification. One checks that the system design works. The other checks that the chip that's meant to go into the system works the way it is expected to, and this is where Cadence and Mentor have concentrated with emulation and, in Cadence's case, with the laughable term "enterprise system level" verification. However, under a banner like "ESL verification" you might expect to see the likes of Calypto, with SLEC (although that might appear under formal verification in the RTL group), and the fast-model builders such as Vast.

Gary has looked at a scenario where 50 per cent of Mentor's sales might disappear through 'leakage' — where fed-up customers defect to the other guys, primarily Synopsys. The figure of 50 per cent seems high but also seem possible but the distribution is likely to be lumpy. I can't see it happening in PCB design, for example, as Mentor's experience with acquisitions is that customers do not like switching tools.

Design-rule checking (DRC) is another area where leakage could well be lower unless Cadence management do something really stupid, such as replacing the people currently driving Mentor's Calibre operation.

However, Cadentor could lose out heavily in some of the bigger markets in which it expects to have a leading position. They are mixed-language RTL simulation and mixed-signal simulation. Given that there is no clean way of merging the tools in these categories, the attrition could be severe. Synopsys would be the direct beneficiary of turmoil in RTL simulators. In mixed-signal, there are some new players who can expect to find that they get into more evaluations than they used to.

In an attempt to make sense of the overlap between Cadence Design Systems and Mentor Graphics, I put together a table of the main product lines with some best guesses about how the combined company would look at them should the takeover go through.

overlap.jpg

The colour coding means the product survives more or less as it is if it's green. Red does not necessarily mean cancellation but indicates where I think it is likely that it will be discontinued and any useful technology rolled into the survivor.

I've basically wimped out on a bunch of them - the ones all in that drab yellow-brown - and put a big don't know on the forthcoming tool Project Sydney as I'm not entirely sure how it overlaps with Catapult. I have put this together on the basis that Cadentor would be more likely to use the Calibre name for the bulk of the DFM tools in the same way that Mentor has even in cases where Cadence's inhouse product has a market share close to that of the Mentor tool.

The biggest question marks are over simulation products, both digital and mixed-signal, and the PCB tools. However, Mentor has demonstrated that is easier to support separate product lines than attempt to move customers to other tools. Cadentor might attempt to push OrCAD and PADS together, but to do the same with Allegro and Expedition could be troublesome.

With the emulators, I would expect Palladium to win out over Veloce simply on the basis that it is the incumbent. However, I would expect Cadentor to let Veloce live out its natural life. That may be the wrong assumption.

The interesting one is Encounter versus Olympus-SoC. I would expect Encounter to win within the company but Olympus has impressed at some chipmakers, so it would probably take some time to disappear under the Encounter name. If the takeover happens, it will be interesting to see whether Cadence considers NanoRoute or Olympus to be the better option.

Update 1: John Busco pointed out that I'd left out ASIC synthesis and static timing analysis. I've now updated the table to include them. Thanks John.

Update 2: Following a comment on other omissions, inFact, Platform Express and Seamless are now on the chart. Have a look at the comments below for the reasoning over how they are placed.

Knight wider

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Assuming Cadence Design Systems' attempted takeover of Mentor Graphics takes a conventional turn, we can expect the Mentor management to put a poison pill or two in place (assuming they aren't already in place - it is something I need to check). And there will be some ringing round looking for an alternative bidder, if only to push the price up.

Some around the electronic design automation industry feel that Cadence's manoeuvres are simply a prelude to a big sale to a hardware company, whether a big chipmaker or the foundry TSMC. I find that argument hard to swallow. Chipmakers have some of their own design tools and the ASIC guys made it big by providing tools to their customers. But the people who fab the chips are in no hurry to own generic synthesis, simulation or layout tools. They sold that lot off years ago. They want to be able to plug their own algorithms and point tools into a ready-made chassis. Cadence's OpenAccess gives them that. They don't need to own Cadence.

TSMC is encroaching on the design-for-manufacturing (DFM) with its own software that is meant to be embedded in the software companies' tools. The move has not been popular with the tool providers because they see it as encroachment. However, there isn't a great deal they can do to stop that without effectively forcing TSMC to snap up one of smaller DFM players. It's hard to see TSMC wanting to own a place-and-route tool and effectively alienate most of its own customers: threatening one half with a lock-in and making the other half feel left out in the cold.

The most plausible bidder for a larger EDA company would be one of the mechanical CAD companies, which leads you pretty quickly to the doorstep of Dassault Systèmes and its Enovia Matrix One operation. But which one would Dassault prefer: Cadentor or Mentor on its own, if either of them?

There is clearly something in the water on the West Coast as hostile takeover fever is taking hold. Away from the Microsoft/Yahoo soap opera, another, somewhat smaller bid battle is gearing up. Mentor Graphics has rejected today's offer from Cadence Design Systems, citing antitrust issues among the reasons:

"As we recently indicated to Cadence, we reviewed Cadence's proposal and analyzed both the price proposed and the risks associated with obtaining antitrust approval for a combination between the companies,” said Walden C. Rhines, chairman and CEO of Mentor Graphics. "Following this review, we concluded that not only was the price insufficient to support a transaction but that the risks of not gaining regulatory approval were sufficiently high that the ability of the parties to consummate the transaction would be in jeopardy. For these and other reasons, our Board unanimously rejected the proposal."

On the conference call, Cadence did not distance itself from the idea that CEO Mike Fister could play the role of Steve Ballmer against who some analysts are setting up as the Jerry Yang in this battle, Mentor's CEO and chairman Wally Rhines. The script is similar: Mentor did not want to negotiate, and is not interested in providing value to shareholders.

Intel came close to giving the idea of having a fixed clock-speed rating on its upcoming Nehalem the heave-ho, according to Intel fellow Rajesh Kumar, speaking to journalists ahead of the VLSI Circuits Symposium in Hawaii this week. The people who were going to be putting the processor into PCs didn't care for the idea, it seems.

The company has radically altered the way that Nehalem is clocked compared with its predecessors in order to improve both memory bandwidth and power consumption. It means that the core, memory buses and I/O run almost independently.

The bigger change is internal, where it seems that the concept of a fixed clock running at several gigahertz has been discarded in favour of letting the logic run at its own speed. This is something that people such as former ARM architect Professor Steve Furber have been advocating for years. The concept of a system clock is entirely artificial and exists largely to make life easy for chip designers and simplify the job of testing chips as they come off the production line. Chips such as the Amulet don't run off any kind of clock: the logic inside finds its own speed.