Fabless: February 2010 Archives

shang-yi-chiang.jpgAt the company’s executive forum held in Yokohama, Japan, TSMC’s senior vice president of R&D, Shang-yi Chiang, provided some background on why yield problems surfaced on the 40nm process — and also some indications that 28nm will not exactly be plain sailing.

Chiang pointed to the shift to immersion lithography — a choice that Intel delayed by a generation — and the use of a new low-k dielectric in the metal layers as the main culprits for the foundry’s problems. He claimed that defect density has reduced significantly since the middle of last year, when chairman Morris Chang decided to expand the team working on 40nm at TSMC.

Chiang said the move from 90nm to 65nm was comparatively simple and the relative cost quite low. “Moving to 45 and 40nm is a lot more challenging,” he said. “This is the first time we began to use 193nm immersion [lithography]. This means the photoresist during exposure is submerged in water and [presents] a very high potential defect [density].”

The low-k dielectric, with a dielectric constant 2.5, was also more fragile than its predecessor. It seems that 40nm was a partial rerun of the 130nm introduction when chipmakers discovered that soft dielectrics and packaging machinery are not the best of mates — the pressure needed to seal the package crushed the metal interconnect.

If you had something like an 80 per cent market share and one of the factors in that was a proprietary language, would you open up the language knowing that this would help competitors turn a foothold into a stronger position? No, I probably wouldn’t either.

But there comes a point where the proprietary language becomes a problem to the customers because it makes it harder to use stuff that has been developed outside that environment. And the customers have to choose between migrating or sticking with what they know and reinventing stuff that they know exists elsewhere. If those customers migrate, then the dominant company loses the reason for holding on to that language - it becomes more of a millstone than an advantage.

In the case of custom and analogue design, the language in question is Cadence Design Systems’ Skill. It’s grown like topsy over the years to the point that even people who’ve worked at Cadence aren’t quite sure what’s in it. Those outside the company don’t stand a chance. But a scripting language like Skill is crucial not only to general custom layout, as it prevents analogue engineers from quietly going mad repeatedly drawing the same shapes over and over again. It also forms the basis of things like process design kits (PDKs) that the foundries provide, as it allows them to define how cells and components are laid out.

Xilinx will for the first time use the same foundry as its main competitor to make its next generation of programmable logic devices and expects to have parts built on a 28nm process by the end of the year.

Xilinx has nominated Taiwanese foundry TSMC as one of the two suppliers it plans to use to make field-programmable gate arrays (FPGAs) on the upcoming 28nm process – which is expected to double density compared to the current 45/40nm-based parts.

Historically, Xilinx has used the world’s second largest foundry UMC as its silicon supplier. Although the FPGA maker has turned to a number of foundries since the 130nm generation, including IBM, Samsung and Toshiba, the company has up to now avoided using TSMC.

Chuck Tralka, senior director for product definition at Xilinx, said when the company looked at how it would move on from the 45nm generation, “we began a survey of process nodes. Originally, we looked at 32nm and then moving to 28nm.”

The company then decided to move straight to 28nm, opting for variants of a high-k, metal-gate process that trade some performance for lower static power consumption, which increases with the number of transistors on a die.

“As we looked out at the process vendors. We began with a survey of what we expect to become available from the various foundries. We began looking with an eye to managing the performance issues. We talked to each of the potential foundry partners,” said Tralka.

“We determined that TSMC and Samsung had the right technology available. We worked with TSMC two years ago and started running test vehicles and began aligning process parameters with internal simulations. We expect to have devices available by the end of the year.

“We are working with both partners: one of them is in the lead,” said Tralka, but declined to say which foundry is likely to have products ready first.

“Both processes are actually fairly similar. They are both high-k, metal-gate and they have similar power/performance characteristics. We work to try to align the processes as much as possible. There are some differences. The families will get tweaked as we prepare to map one for each process or another.”

“What we will be doing is mapping particular families into particular fabs. And aligning what we think are the best power-performance trade-offs.”

Tralka claimed the long-standing relationship between Altera and TSMC “is not that big a concern. It is something that we have thought about. But TSMC does a good job working closely with each of their partners without compromising the work of their partners.

“Our foundry has been a multi-foundry strategy. We are a larger company company and we need more capacity available to us. And our strategy has been to choose the best partners for each node rather than wedding ourselves to a single process partner,” Tralka explained. “It’s possible that we will make different choices in future generations.”

The next generation of FPGAs from Altera won't be quite as programmable as the last - although you will be able to flip some of the logic inside them as they run. For the generation of FPGAs to be made on a 28nm process, Altera is making several changes.

One change is the merging of HardCopy - the mask-programmed gate array used to provide fixed versions of customer design for less money per die - with the mainstream programmable logic family of Stratix parts. Another is the decision to finally adopt partial reconfiguration so that parts of the logic can be switched in and out while the rest of the system is still running.

"Partial reconfiguration has been around for a long time," said David Greenfield, senior director of Altera's HardCopy business unit. "But this is a fairly significant shift for Altera."