Fabless: May 2009 Archives

In his keynote at the recent Design Automation and Test in Europe conference, ARM CTO Mike Muller spent a little bit of time to say thank-you for some of the electronic design automation (EDA) tools out there. One perhaps unexpected beneficiary - because it usually gets no respect - was design for test (DFT).

Indeed, when DFT engineer John Ford spotted how Mentor Graphics' Joe Sawicki referred to the technique as being instrumental to the future of chipmaking on Twitter, John Blyler of Chip Design magazine, and probably others, thought it a little strange. As the man who has headed up Mentor's design for manufacturing (DFM) strategy for more than ten years, surely Sawicki meant that, and not DFT?

For Muller, DFT or test automation makes it possible to test chips. "We couldn't have hand-stitched all those scan chains," he said. But lots of EDA is about automation. The other aspect of DFT that has emerged in the past few years is its role in yield prediction and planning, and Muller very briefly alluded to this use for DFT. As yield more or less equals profit (assuming you're not in dumping territory), it is easy to believe that DFT has a crucial role in chipmaking.

I'd link to an interview I did with Mentor's chief scientist and test expert Janusz Rajski several years ago, but it has effectively disappeared offline. So, the rest of this post is that interview. I have done a more recent interview with him but but it hasn't been published as yet, so I'll do a follow-up with changes. Hopefully, this should go some way to explaining why some people in the chip-design business suddenly love DFT. This is the pre-edit copy, so there might be some typos in it - I just took one out.