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STMicroelectronics expects to put its first 20nm process into production at its Crolles fab in France by the end of 2012 after completing a programme to catch up on internally produced processes with the major foundry suppliers.

Although the company expects to increase the amount of production that it outsources to foundry from its current level of 15 per cent to 20 per cent long-term, ST decided recently to put more investment into Crolles in a bid to quickly move to parity with the processes supplied by the major foundries and to be able to build its own derivative processes, such as the recently announced 32LPH process which uses a high-k metal-gate transistor structure.

Jean-Marc Chery, CTO of ST told analysts at the company’s annual Field Trip: “I am confident we will be able to to tape out in our 20nm low-power process the first product by Q4, 2012. This will gain more 30 per cent performance and a 2x shrink factor [over the previous process technology].”

Chery said the company is prototyping with its 32nm process and expects delivery of its first production immersion scanner next week so that production can ramp up in the third quarter of next year. This process ramp will follow just one quarter after the ramp for its low-power 40nm process. The 45nm process will ramp up in the fourth quarter of this year.

TSMC has said it will ‘skip’ the 22nm process node as its next step on from the 28nm process that is due to roll this year. However, it might just be rounding error based on past performance, as the company is aiming for a ‘20nm’ process.

This will be the third round of the Taiwanese foundry’s attempt to demonstrate that it is ahead of the process curve compared even to Intel, which went into volume production with a 32nm process at the end of last year. However, as with TSMC’s 28nm and 40nm processes, it’s hard to know how this will compare to the 32nm and 45nm nodes that appear on more conventional roadmaps. With games like these, it’s easy to see why the International Technology Roadmap for Semiconductors (ITRS) gave up on the idea of naming nodes. Instead, it focuses on actual on-silicon measurements in its estimates of when processes will become available.

Based on what TSMC presented at conferences in recent years, the 40nm process has measurements such as contacted gate pitch - the key one for transistor density - which were consistent with Intel’s more conventional nomenclature. One library supplier pointed out that TSMC’s 40nm process was pretty much its 45nm process but with more restricted design rules.

Until IEDM rolls round at the back end of this year, TSMC is unlikely to publicly disclose the reality of its ‘20nm’ process, although big customers will know what they’re dealing long before that.

What will be a plus point for TSMC, although it sounds a little strange, is that the company will almost certainly be enforcing highly restricted design rules in the 20nm process - but this will be the third iteration of that move. Because of its use of a gate-last manufacturing process at 28nm, similar to the approach used by Intel since 45nm, TSMC already needs to make sure designers use a small selection of shapes in their standard-cell libraries. Gate-last manufacturing tends to provides opportunities for strain engineering but with the downside of being less tolerant to design variation.

As there is no plan to move to extreme ultraviolet and the technique of source-mask optimisation is also on the table - in which the shape of the light beam is tuned to the on-chip structures used on the finest geometry layers - it is going to be straight lines all around as far as chip design is concerned. But much more of the infrastructure for designing that way will be in place by 2011/2012 (as initial production is meant to start at the end of 2012).

TSMC is confident that anyone using gate-first right now will have to switch to doing it the other way real soon now even if their customers have had a bit more freedom in the design department. I guess TSMC sees it as an advantage in saying they have ‘leapfrogged’ the competition in measurements even though it’s the same kind of trick the other camp can do. They have already done the trick of launching a 28nm half node hot on the heels of the originally planned 32nm version of the process. There is plenty of time for Common Platform foundries to turn up and say: “Oh look what we’ve found, a 20nm process.” They might as well call their processes Turbo and Super for all the good this grade inflation does. People doing chip design will have other metrics they are worried about.

What's old is new again

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SSMC fab, SingaporeYesterday, Singapore-based foundry SSMC celebrated its tenth anniversary of silicon manufacture with the news that it was to spend $30m — split roughly 50/50 between R&D and manufacturing — to extend the fab’s lifetime. The investment is meant to keep SSMC’s 200mm production lines relevant in a business now dominated by plants that process larger wafers and which should be more cost-effective.

“We are putting in place a vision that ensures SSMC is in a good position for the next decade or two,” said CEO Jagadish CV.

Jointly owned by NXP Semiconductor and Taiwanese foundry TSMC, SSMC was one the last big 200mm digital logic-oriented fabs to be constructed, opening just ahead of the dot-com crash. It produced the first yielding silicon in October 2000, so barely turned in a quarter’s worth of production wafers before the slump.

After the recovery, 300mm production with 0.13µm copper processes had pretty much taken over from 200mm, which because of the decisions made by production-equipment makers, were stuck on 0.15µm and larger linewidths and aluminium metal interconnect.

Rather than throw in the towel, SSMC changed direction, concentrating on ‘ABCD’ products — analogue, bipolar, CMOS and DMOS. Basically, stuff that wasn’t the standard CMOS turned out by 300mm fabs owned by TSMC and others.