Chipmaking: April 2010 Archives

TSMC is to break ground on its third major 300mm (12in) fab in the middle of this year, the company said as it released slightly better than expected results for the first quarter of 2010. With the existing 300mm plants, Fab 12 and Fab 14, nearing their planned maximum capacity of 100 000 wafers per month, it’s time for a new one.

As it will take at least a year to build the shell, Fab 15 - which was originally earmarked for Tainan rather than its revised location of Taichung, roughly midway between TSMC HQ in Hsinchu and Tainan, before the chip market imploded in 2001 - will not play much of a role in TSMC’s production before 2012.

When it gets going, chairman and CEO Morris Chang, said Fab 15 will support capacity expansion for the 40nm process and will add 28nm before moving onto the 20nm technology and beyond.

In the meantime, TSMC is rushing to get more equipment into Fab 12 and Fab 14, pushing 300mm production up by 35 per cent by the end of the year. However, Chang said these fabs are nearing their planned maximum capacity of 100 000 wafers per month. The company plans to use the majority of its capital expenditure for 2010 in the first half of the year to ensure much of the extra capacity is in place by the end of 2010.

Older 200mm fabs are not to be left out of the expansion - Shanghai, in particular will see new equipment for the “more than Moore” programme the company adopted to keep its older fabs running.

TSMC saw a modest rise in sales from the fourth quarter of last year to the first quarter of 2010 rather than the expected post-Christmas dip.

CFO Lora Ho said: “Contrary to expectations, first quarter revenues and wafer shipments slightly increased.” The growth was driven by communications and consumer products, coupled with stronger demand on the recently introduced 40nm process, helped by improving yields.

Chang said yields on the 40nm are now as good or better than those encountered on the previous 65nm process at the same stage of its development. In the first quarter, the foundry sold $411m worth of wafers to customers made using the 40nm process – revenues from the 65nm process passed the $400m point two years ago.

“Combined revenue from 40nm and 65nm processes accounted for 41 per cent of total wafer sales,” said Ho.

Phase-change memory (PCM) has been gestating for close to 40 years but Numonyx has come up with devices that can begin to take on NOR flash in embedded systems designs. By the end of the year, the company reckons it will have ready denser devices that will suit mobile-phone makers.

Numonyx has pushed the write endurance of 128Mbit phase-change memory (PCM) devices to the point where it is now ten times that of typical flash memories and has launched a family of parts to replace DRAM and flash in embedded systems. The company is now working on higher-capacity memories to go into future cellphone designs, agreeing to use the same interface as competitor Samsung.

Giuseppe Crisenza, vice president of strategic alliances for Numonyx, said the company has been optimising the technology on a 90nm process since it launched the first memories in late 2008. In that time, the write endurance increased from 100,000 to 1 million cycles.

Because flash memories have lower cycle counts they need to use techniques such as wear levelling to prevent overused bits rendering the devices useless. PCM devices have the further advantage of allowing individual bits to be written unlike flash memories that have to be erased in blocks and rewritten.

Numonyx will sell both serial- and parallel-interface versions of the 128Mbit PCM, aiming mainly at the general embedded market rather than the mobile-phone business, although Crisenza said there are low-end mobile phones for the Asian market that could use the devices.

“There are a lot of applications that for cost reasons prefer the serial interface,” said Crisenza.

TSMC has said it will ‘skip’ the 22nm process node as its next step on from the 28nm process that is due to roll this year. However, it might just be rounding error based on past performance, as the company is aiming for a ‘20nm’ process.

This will be the third round of the Taiwanese foundry’s attempt to demonstrate that it is ahead of the process curve compared even to Intel, which went into volume production with a 32nm process at the end of last year. However, as with TSMC’s 28nm and 40nm processes, it’s hard to know how this will compare to the 32nm and 45nm nodes that appear on more conventional roadmaps. With games like these, it’s easy to see why the International Technology Roadmap for Semiconductors (ITRS) gave up on the idea of naming nodes. Instead, it focuses on actual on-silicon measurements in its estimates of when processes will become available.

Based on what TSMC presented at conferences in recent years, the 40nm process has measurements such as contacted gate pitch - the key one for transistor density - which were consistent with Intel’s more conventional nomenclature. One library supplier pointed out that TSMC’s 40nm process was pretty much its 45nm process but with more restricted design rules.

Until IEDM rolls round at the back end of this year, TSMC is unlikely to publicly disclose the reality of its ‘20nm’ process, although big customers will know what they’re dealing long before that.

What will be a plus point for TSMC, although it sounds a little strange, is that the company will almost certainly be enforcing highly restricted design rules in the 20nm process - but this will be the third iteration of that move. Because of its use of a gate-last manufacturing process at 28nm, similar to the approach used by Intel since 45nm, TSMC already needs to make sure designers use a small selection of shapes in their standard-cell libraries. Gate-last manufacturing tends to provides opportunities for strain engineering but with the downside of being less tolerant to design variation.

As there is no plan to move to extreme ultraviolet and the technique of source-mask optimisation is also on the table - in which the shape of the light beam is tuned to the on-chip structures used on the finest geometry layers - it is going to be straight lines all around as far as chip design is concerned. But much more of the infrastructure for designing that way will be in place by 2011/2012 (as initial production is meant to start at the end of 2012).

TSMC is confident that anyone using gate-first right now will have to switch to doing it the other way real soon now even if their customers have had a bit more freedom in the design department. I guess TSMC sees it as an advantage in saying they have ‘leapfrogged’ the competition in measurements even though it’s the same kind of trick the other camp can do. They have already done the trick of launching a 28nm half node hot on the heels of the originally planned 32nm version of the process. There is plenty of time for Common Platform foundries to turn up and say: “Oh look what we’ve found, a 20nm process.” They might as well call their processes Turbo and Super for all the good this grade inflation does. People doing chip design will have other metrics they are worried about.