Chipmaking: March 2010 Archives

What's old is new again

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SSMC fab, SingaporeYesterday, Singapore-based foundry SSMC celebrated its tenth anniversary of silicon manufacture with the news that it was to spend $30m — split roughly 50/50 between R&D and manufacturing — to extend the fab’s lifetime. The investment is meant to keep SSMC’s 200mm production lines relevant in a business now dominated by plants that process larger wafers and which should be more cost-effective.

“We are putting in place a vision that ensures SSMC is in a good position for the next decade or two,” said CEO Jagadish CV.

Jointly owned by NXP Semiconductor and Taiwanese foundry TSMC, SSMC was one the last big 200mm digital logic-oriented fabs to be constructed, opening just ahead of the dot-com crash. It produced the first yielding silicon in October 2000, so barely turned in a quarter’s worth of production wafers before the slump.

After the recovery, 300mm production with 0.13µm copper processes had pretty much taken over from 200mm, which because of the decisions made by production-equipment makers, were stuck on 0.15µm and larger linewidths and aluminium metal interconnect.

Rather than throw in the towel, SSMC changed direction, concentrating on ‘ABCD’ products — analogue, bipolar, CMOS and DMOS. Basically, stuff that wasn’t the standard CMOS turned out by 300mm fabs owned by TSMC and others.

When Swiss startup Innovative Silicon first got going, the company argued that its memory technology could be the thing that drives people towards silicon-on-insulator (SOI) wafers. Despite a strong push by companies such as AMD and IBM, SOI remains a minority choice. All the rest of the action is on bulk silicon wafers.

Following a shift from trying to license its one-transistor memory technology for use alongside logic transistors on system-on-chip (SoC) devices - AMD was the first major licensee — ISi decided a year or two ago that it had a better chance of getting DRAM makers to adopt it before trying to tackle the embedded-memory market again some time in the future.

The DRAM makers have had to come up with increasingly exotic ways to squeeze the bit-storage capacitor into tighter and tighter spaces. ISi is betting that one day real soon now, space is going to win that battle.

By storing a much smaller charge in the body of a transistor, ISi’s Z-RAM could potentially save space — you only have to have a 1T cell, not a 1T-1C cell as with conventional DRAM. But DRAM makers are not in a hurry to move to SOI — they like their wafers to be cheap.

So, ISi has moved in the other direction: away from SOI and into bulk silicon.

crolles-cleanroom.jpgSTMicrolectronics has recruited US-based EDA company Mentor Graphics to a French R&D programme as part of a plan to have processes down to 20nm running at Crolles by the time the programme finishes in three years.

The Nano2012 programme originally included just ST and its fab at Crolles and the CEA-Leti research institute based nearby in Grenoble. But, with ST having joined the IBM alliance of companies developing sub-45nm processes, the Nano2012 programme has become more international in scope. IBM joined the team with Dutch lithography equipment maker ASML also opting to become part of the programme.

On the conference call to discuss the deal, Mentor president Greg Hinckley was keen to stress the company’s French credentials. The EDA vendor has more than 100 engineers based in the country and will recruit a further 20 to work on the DeCADE project that forms part of the Nano2012 programme. But the deal means a bit more than R&D jobs in France.

The project will include the development of a 28nm chip within two years that will be made at Crolles. By joining the programme, Hinckley said Mentor will have unprecedented access to real-world issues in design with advanced processes. It provides “an opportunity to try out ideas and algorithms”, Hinckley said. “Mentor will be able to immediately validate EDA techniques for 28nm and below and critical, adjacent technologies such as mixed-signal, RF and 3D packaging.”

chip-profit.jpgIndustry analyst firm iSuppli has run the numbers on companies in the semiconductor business and found they are turning in levels of operating profitability not seen since the glory days of the Internet boom.

Overall operating profitability rose to 21.4 per cent according to iSuppli in the fourth quarter of 2009, the highest level since the last quarter of 2000. Those working around the industry then will remember those heady days, which were quickly followed by a sudden post-Christmas hangover when purchasing managers staggered into their warehouses and wondered: “Cripes. Did we really order all this stuff?”

For those thinking that the world was only just beginning to move out of recession late last year, a lot of the recovery in profitability in chipmaking has come from very aggressive supply management, also known as not spending anything on stuff to make chips with. Major customers are now in the unusual position of not being able to name their price and it’s not going to get any easier for them any time soon even though the big chipmakers are now opening up their wallets to expand production capacity.

wafers-price.jpgEven during the disastrous first quarter of 2009, prices did not fall as far as they used to — because the chipmakers did not allow inventory to build up in the way it did in 1995 or 2000. In fact, prices went up for a while before falling slightly as the recovery got under. This is very different to what happened in 2001 when prices went down and kept going down. The revenue per wafer (red line) and wafer output (grey area) chart here from SICAS and SIA numbers shows what happened.

President and CEO of iSuppli Derek Lidow also cited the increasing focus of chipmakers: “The semiconductor industry has almost completely eschewed the broad-line model that once was the hallmark of the largest players in the business. Instead, chipmakers now are concentrating on specific market segments, allowing them to focus on areas where they have pricing power and a competitive advantage. This has allowed them to improve profit margins and to cut overhead.”

That position echoes former Infineon president Wolfgang Ziebart at Electronica in 2006: “Before, size was very important. This is over.”

At the same panel session, Professor Hermann Simon of Simon-Kucher and Partners went a bit further by chiding the chip industry for being “stupid” by chasing market share, and constantly dumping price to get it.

Infineon’s board thanked Ziebart for his insight by firing him and then wound up shutting down Qimonda just months ahead of a pricing recovery that might have helped the German memory maker find a buyer as a going concern rather than a source of cheap production tools for Texas Instruments.

The numbers for the second half of the last decade don’t really bear out Lidow’s assertion. Profitability fell to a lower sustained level from 2006 onward and really only took off after fab managers decided the best way to cope with the worldwide financial crisis of late 2008 was to turn a lot of machinery off. However, looking into the future, vanishing sockets and increasing focus should demonstrate what Lidow describes in the medium to long term.

Foundry mix

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foundrymix.jpgThis is the last time a graph like this will appear for a while. Because Chartered Semiconductor Manufacturing is now part of Globalfoundries there won’t be an opportunity to get information on the processes the company is running from financial reports. AMD will only report profit or loss in its figures now that the company has switched to equity accounting even though AMD holds the lion’s share of the key stock class that determines overall ownership.

Now that the results are in for 2009, it’s possible to see what effect the semiconductor industry’s bungee recession (thanks to Future Horizons’ Malcolm Penn for the inspiration for the phrase) has had on the shift towards more advanced processes. What’s interesting about the first set of charts is that you’d hardly know the foundries practically turned their machines off for a couple of quarters.

Utilisation plunged to 30 per cent in the dark days of early 2009 before bouncing back to near capacity by the middle of the year. Had it not been for TSMC’s 40nm yield problems, the transition towards 40/45nm processes might have been a bit quicker. But the severity of the recession arguably gave the number-one foundry a bit of breathing space, arguably helped by the better yield on more expensive flip-chip packages that the 40G-process chips would typically go into.

baolab-metal-mesh.jpgMicromachined chips promise much, which is why every time they turn up in a new system — such as the Nunchuk controller in the Nintendo Wii or the motion sensor in the iPhone — it’s tempting to herald a new dawn for MEMS. It’s invariably a case of “this time it’s all going to happen for MEMS”.

But some big problems still face MEMS. It’s not as cheap to make as you’d expect and the one thing you’d expect manufacturers would have down to a fine art — integration with other microelectronics — is still not easy to do. It’s even hard to package the things. They often need to be carefully sealed using special caps to stop moisture disrupting their delicate inner workings.

The seven-strong team at Barcelona-based startup Baolab reckon they have an answer to at least some of these problems. Having already developed a novel type of MEMS structure — basically a floating bar in an electrostatic box — several years ago, the company was faced with the problem of making it commercially viable.

A column in PC World on the launch of nVidia’s Next-Generation Ion (or Ion2 as a lot of people call it) decries the way that the graphics processor (GPU) company has backed away from Ion being a ‘platform’ into just being an additional chip for Intel’s own Atom chipset. There isn’t a whole lot that nVidia can do about that. Welcome to the land of disappearing sockets.

While people speculate on why Intel and TSMC have so far failed to get anyone into production with an Atom system-on-chip (SoC), the one company with a real reason for licensing the processor core finds its latest creation dangling off the end of a PCI Express bus provided by Intel’s Pine Trail chipset.

When Intel launched the first generation of Atom, it was a tiny sliver of silicon that relied entirely on other chips to control a PC. Although you pretty much had to buy the Atom with its support chips from Intel, nVidia encouraged PC makers to dispense with the standard chipset and replace it with the Ion and its built-in graphics.

With Pine Trail, Intel decided to move its own GPU and main memory controller into the Atom processor itself and sell a smaller peripheral controller ‘South Bridge’ device, leaving nVidia with far less scope to have an influence on what an Atom-based PC would look like inside.

Steve Teig pictured in front of several Tabula die-plotsI think the only sane advice I could give anyone on whether to start up a programmable-logic company today is: “I wouldn’t start from here if I were you.”

Perhaps the best response is to come up with what is, at first glance, the most insane architecture I’ve ever seen. Even its creator concedes that your best bet is not to think to what’s going inside because it gets too hard to conceptualise. Even the tools that build the design on Tabula’s architecture don’t deal directly with what happens inside the device.

Tabula is president and CTO Steve Teig’s fifth startup. Two were in electronic design automation (EDA) — the most recent being Simplex Solutions, which sold to Cadence Design Systems — and two in biotechnology. Even he spent a while, after leaving Cadence in 2003, wondering whether starting an FPGA company was a wise move considering the trail of dead companies that has formed in the wake of Xilinx’ and Altera’s dominance of the market since the early 1990s.

The company’s CEO, Dennis Segers, was responsible for the Virtex architecture at Xilinx — the company’s top-selling family of FPGAs — and was the man venture capitalists hauled in whenever they had a potential investment in an FPGA startup to make. And those VCs have not been short of choice in the past decade. Neither have they done very well out of it. Segers didn’t rate any of them.

At the TSMC 2010 Executive Forum, Yoji Hino from Fujitsu talked about the company's move to a fab-lite operation with the shift to 28nm. Although the Japanese company has its own fabs able to turn out 40nm devices, it will use TSMC for 28nm production.

One issue that Hino covered was the impact that the I/O ring has on device scaling from 40nm to 28nm. Unless you stuff the device full of transistors the I/O ring on wirebond devices can quickly dominate the cost because the pads don't scale anywhere near as fast as SRAM cells and logic gates. Analogue also generally doesn't benefit that much from scaling, except in terms of switching speed.

Hino presented a chart that showed good scaling from 65nm to 40nm for a device with 20 million gates of logic and 15Mbit of SRAM plus some analogue. On a 65nm process, this measures 10.1mm on a side. On a 40nm process, the dimensions reduce to 7.3mm on a side, a reduction of 48 per cent. However, the increasing dominance of the I/O ring and the analogue means that the 28nm device sees a slightly smaller reduction in area: 41 per cent for a chip that is 5.6mm on a side.

To stop the I/O ring from being too much of a burden, Fujitsu and Toshiba are cutting the pad pitch from 25µm to 22.5µm for staggered pins. The single-row pitch will drop from 40µm to 35µm. As smaller devices on 40nm could benefit from a reduction in I/O pitch, the older process will, apparently, also have the smaller staggered-pin dimensions from the end of the year, when 28nm is supposed to go live. The single-row pitch on 40nm will remain unchanged, presumably on the assumption that if a device is only using a single row of pins around the edge, it's hardly going to be pad-limited.