Chipmaking: December 2008 Archives

At first glance, the 40nm process presented by Toshiba at IEDM last week looks no great shakes. In a session dominated by 32nm processes, this one seemed not just one generation behind but a bit more than that if you compared its headline figures with the 45nm technologies described by Intel and TSMC in 2007. But a closer inspection reveals a process with a bit more going for it.

When Toshiba says it's a 40nm, the company means the gate measures 40nm. This is a good 30 per cent longer than the minimum gate length quoted by Intel and TSMC last year and puts the transistor more in line with a 65nm or 55nm process – actual gate length has outpaced the notional length contained in each node's title for some years. As a result, figures such as current drive, which control the performance of the core transistors, are lower than those quoted by TSMC. The NMOS transistor of Toshiba's high-speed version of the process has a current drive of 840µA/µm, around 30 per cent worse than the process that turned into TSMC's own shot at a 40nm technology.

But, if you compare with a 65nm process, where transistors often wind up in the 40nm-long range, Toshiba's numbers are par for the course. The bulk technology covered by IBM and the Common Platform partners at IEDM in 2004 shows broadly similar numbers. More importantly, the leakage in the new Toshiba process is lower than in those older processes thanks to the decision to implant nitrogen atoms in the transistor channel, the use of flash-lamp annealing and just a touch of high-k in the gate over the channel, without going all the way to high-k, metal-gate structures.

TSMC pulled a switcheroo at the International Electron Device Meeting (IEDM) in a further piece of technology oneupmanship following on from its claim of an early move to 28nm earlier in the autumn.

Director of advanced process development Carlos Diaz was scheduled to talk about the company's 32nm high-k, metal-gate process - one that does not actually appear on TSMC's official roadmap now that 28nm has supposedly taken over. The official proceedings are all about the 32nm process. But when Diaz took to the stage, it was a different story: he was there to describe what the company had done with its 28nm process.

This time, there was to be no confusion similar to what happened with the 45nm process where, by the time TSMC launched it commercially, it had transmuted into a 40nm. This 28nm process has different measurements.

Now, is it really a 28nm process? It depends on how you look at it. I think Kaizad Mistry of Intel was right last year when he said contacted gate pitch is the critical measurement that determines how dense a process can be. And density is the reason why people move to more advanced processes. But, you could also argue that SRAM cell size is just as important, especially now that most chips have big banks of the memory on-chip.

If you look at contacted gate pitch, then what TSMC calls a 28nm process would be a 32nm process at Intel. Diaz reported a pitch of 117nm at IEDM on Wednesday. Intel's late paper on its 32nm process came in with a figure of 112.5nm.

Intel, however, has been more conservative with the SRAM cell the company proposed. However, there is a fair amount of latitude in this metric as there is a clear trade-off between size and noise. The smaller they get, the more noise you see in the SRAM circuits. Too much noise and the circuits begin to fail. TSMC pushed to get a cell that measures 0.13µm2. Intel was happy with 0.17µm2

It was a similar story last year in the duel over 45nm, where TSMC showed a smaller SRAM cell but its gate pitch was not as tight as Intel's. This time around, TSMC wants to demonstrate that it has a disinct 28nm process but there is still a question mark over whether this 28nm is not simply a tight 32nm.

When I last interviewed Wilf Corrigan, before he moved up to chairman and ultimately parted company with LSI Logic, he argued that the Japanese chipmakers made one crucial mistake in the 1990s. They didn't trust chemical mechanical polishing (CMP).

I have a lot of sympathy for the Japanese technologists. If someone came to you and said: "We know you've taken a lot of care to put down those transistors. They're incredibly delicate structures. That's why we think you should go at the wafer with a Brillo pad and a bucket of acid."

In essence, CMP is a high-tech scouring process. You lower an abrasive pad onto a spinning wafer and you add a chemical slurry and you keep going until you think the wafer has been polished flat. Believe it or not, this works. CMP flattens surfaces other techniques cannot reach. Before CMP, the top surfaces of chips were lumpy affairs. Each layer you put down made it lumpier. It meant there was a limit to how much wiring you could get on the chip. Three layers and you were about done. A section through a chip looked more like a geological diagram of what rock strata look like after a few earthquakes.

The industry could not stick with three layers, they had to go higher. But they had to deal with the lumpiness. The answer was to take the scouring pad to the wafer after putting down another layer of metal. Believing that they could not control the quality of the polishing, the Japanese held back. But the US companies pressed on and started to retake a lead in chipmaking they lost ten years previously.

Intel reckons CMP can do a lot more. And Joseph Steigerwald turned up to IEDM in San Francisco to let them know what. There is an Intel-oriented subtext to his paean to the high-tech Brillo pad: it's a key component of the process used to make the metal gate stacks in the company's 45nm process and, most likely, the 32nm version. Where the rest of the business is focusing on the gate-first approach, Intel reckons that its approach works better. And CMP makes it possible.

The other place where CMP is going to be crucial is going to be in 3D integration, particularly where chips are bonded together and connected using metal vias that extend all the way through the wafer. And this is where another surprisingly reliable technology, reactive ion etch, plays a big role. Etching is arguably one of the most precise tools available to process engineers even though it revolves around pumping noxious gases into a chamber where they can start eating into the silicon. Luckily, those gases don't eat away at the hard masks that seal off portions of the wafer.

For things that look as though they really shouldn't work, CMP and etching have done pretty well for themselves.