Researchers at MIT have developed a way to draw lines on wafers that are just 25nm across and spaced 25nm apart much more cheaply than today's fancy immersion lithographic steppers. The bad news is that the $2m tool developed by Mark Schattenburg, Ralf Heilmann and two graduate students at MIT can only do parallel lines right now. But the technique could provide an alternative way of doing double patterning that could potentially push optical lithography well into the next decade.
The technique, which is based on the 'nanoruler' developed a few years back, uses interference patterns generated by pumping 100MHz sound waves into a crystal through which they shine a laser beam. Heilmann said: "We use a transducer to change the properties of the sound wave at a very fast rate. We have updates rates of 10kHz or so. Changing the sound wave changes slightly the phase of the light wave that goes through the crystal."
By recombining the light split from a laser under the control of vibrating crystals, it is possible to create very fine interference patterns. These produce extremely thin lines on the wafer. The researchers worked with a laser operating at a wavelength more than 50 per cent longer than the 193nm deep-UV light used by today's steppers. But the interference pattern leads to sub-30nm lines. But they are quite widely spaced: about 200nm apart.
To get the line density up, the team used four passes. This takes time but Heilmann said the process can be applied across a wafer rather than being limited to a 600mm2 reticle.
In its current form, the scanning-beam interference lithography can only make parallel lines. “We are working on changing the optical design to do a greater variety of patterns,” said Heilmann.
Although the technique might be used to create just regular structures, one possibility is that interference lithography might be combined with conventional lithography. For starters, companies such as Intel have already started to use more regular structures. In this approach, long lines could be patterned across the surface of the wafer and then cut into gates, for example, using an existing stepper. Very often, silicon transistor gates are way, way wider than they are long. And this pattern-and-cut trick is an approach that Intel already uses with conventional steppers on the 45nm Penryn devices.
One issue for the future is that of line-edge roughness. This roughness is becoming more and more of a headache because it increases the variability of transistors. Just cutting that variability in SRAM transistors, which tend to be more densely packed than others on a typical chip design, could pay off in better yield.
"Line-edge roughness is not a limiting factor but it is close to being one," said Heilmann.
Schattenburg said in the release: "There are several new technologies on the horizon that have the potential for alleviating these problems. These results demonstrate that there's still a lot of room left for scale shrinkage in optical lithography."