Chris Edwards: June 2009 Archives

Gary Smith has put out a brief note on the latest round of layoffs at troubled Cadence Design Systems. He writes that the cuts are not as deep as expeced, indicating that the situation at the company is recovering.

The problem, Smith remarks, is with the cuts in the design-for-manufacturing (DFM) tools division. Cadence claimed that the cuts are mainly aimed at the manufacturing side of this, which is where the company is way behind Mentor Graphics and Synopsys. The cuts do not directly affect the IC layout tools, which has been a core part of the Cadence portfolio since the company formed.

But Smith points out that DFM is being pulled into the IC layout space. The tools that do the layout need to understand some elements of what happens in manufacturing as those effects become more prevalent in the more advanced processes.

Speakers at the recent International Conference on CMOS Variability organised by the UK's National Microelectronics Institute pointed out that the environment around a standard cell in 45nm and 32nm processes now affect how the transistors inside the cell perform. Above 130nm, each transistor was an island. At 90nm and 65nm, library designers had to start worrying about the relationships between transistors within the cell. Now, it makes a difference which cells you put next to each other - and that's a problem for the placement tool.

I agree with Smith's argument that, if you cut back on the manufacturing side of DFM, you lose some of the skills needed to keep your layout tools on top. I'm pretty sure Aart de Geus, CEO of Synopsys, is aware of this and is probably why he is giving keynotes emphasising how important it is to have tools that work closely together, or maybe even rolled into one lump of code in the same way that simulators combined logic and analogue circuit code.

At the GSA and IET International Semiconductor Forum, de Geus talked a lot about how tool interoperability. "None of the tools can work in isolation anymore," he claimed. "In the 1990s, the issue was one of dataflow. From 2000 to 2005, it was all about correlation. From 2005 to 2008, tools needed to look ahead to see what is downstream. In 2009, it is a continuum. We see a massive integration, a move towards complete flows as the only way to deal with all this complexity."

However, two thoughts entered my head as I heard an EDA CEO go hard on the integration sell. If you recall, Cadence under Mike Fister was all about selling one flow to rule them all and did not do so well at it. It's an argument that plays well with Wall Street because the finance community find it easy to assign a value to a monopoly strategy.

Back in the real world, although engineers understand there is value in having a primary vendor around which you can build a design flow, no-one believes that any of the current EDA companies actually have one flow that spans even IC layout to DFM. The chances are pretty good that even companies using Synopsys for layout probably have Cadence Virtuoso for custom and library design and Mentor Graphics' Calibre for design-rule and DFM checks.

The second was thought was a reminder from history. Monterey Design Systems tried to build a holistic layout tool that weighed up everything at once. All it did was weigh down the tool. I'm not sure anyone in a chipmaker ever got to evaluate Dolphin in any depth - I met a couple of CAD managers who were waiting for it but they wound up buying Magma's offering if not the one from Cadence or Synopsys.

The idea of having some kind of do-it-all layout tool sounds good but, from what I've seen time and again in the history of EDA is that most of the time you don't need that level of detail. You need to zoom in where it matters and ignore the effects where they don't. A lot of the time, the speed of an individual transistor is immaterial because the circuit in which it sits never has to run that fast. You can get problems with things switching too quickly and with fast paths that come up against a slow transistor. But the trick is to identify likely problems and focus all the effort on those. For many other cases, abstraction works just fine.

However, if you don't have the tools inhouse to work out which bits might be messed up, you are in trouble. In an ideal world, you've have heuristics to identify the troublespots and call up a more accurate tool to do some doublechecking. And it should not matter whether this is your own tool or someone else's. Unfortunately, the big EDA companies have worked hard to close down interoperability except where they really needed to support it. And the big two embarked on sales strategies calculated to wipe out the previously fertile coral reefs of the tools businesses, populated by small specialised startups.

In the Open Access database, Cadence at least built a technical infrastructure that could support an environment based on specialised tools working together. But without the commercial will to open up, only a few were prepared to join in. Cadence could well do with a reef of keen specialists to fill out holes that are opening up in its own portfolio. But will the company realise this too late? Let's face it, Synopsys is not going to be in a hurry to help. And Mentor may decide it is far enough down the road with the combination of Olympus and Calibre to not care either.

Cadence can retrench into verification and try to maintain its hold on the Virtuoso customer base. But, Smith lays out out the figures. Chip layout plus design-rule and DFM work was almost two-thirds of the EDA business in 2007. It's probably even more now. And in verification, the money is evenly split three ways. That's a much smaller Cadence you're looking at long-term unless the company can find a way out of its bind in IC layout.

Two of the standards-creating bodies around EDA have decided to merge their operations. By the end of the year, Accellera and the Spirit Consortium expect to have thrashed out all the details needed for the actual merger between the two groups to take place next year, after the end of their respective financial years.

Shrenik Mehta, chairman of Accellera, said the organisation had been looking harder at developing standards around IP for chip design. "IP has become a more important component. We looked towards the future and how work in this area could benefit the industry. Spirit was a complementary effort and we felt that if we merged together we would get a stronger organisation that can address the industry’s needs, covering the entire spectrum of design verification and IP reuse," he claimed in a phone interview.

The combined group, which will keep the Accellera name, will derive some savings. And Spirit, which plans to hand off version 1.5 of the IP-Xact IP-description standard to the IEEE will benefit from the experience of an organisation that has been through that process a few times now.

At DAC, the Accellera and Spirit board representatives expect to be able to tell their respective memberships how the merger will pan out and what changes will have to be made in the combined organisation. Ralph van Vignau, president of Spirit and who has been driving the group enthusiastically since the idea first got off the ground around the middle of the decade, reckons the process should be reasonably straightforward as the working methods are not all that dissimilar.

There are likely to be some differences, but this is one of those deals where the interests of the two groups align pretty well. The merger will probably help garner more interest in IP-Xact among US-based companies. A number of the bigger multinationals have embraced IP-Xact but the difference in awareness of the Spirit IP-description scheme across the Atlantic is still palpable - it's better known and understood in Europe, and I believe in Japan, than in the US. The companies who haven't looked at it are missing out.

At DATE this year, engineers from ST-Ericsson gave a good description of how they use IP-Xact to ease the job of building prototypes of SoCs on programmable logic. IP-Xact was never designed to support that but when you've seen someone show how they did it, you realise how effective the database format can be.

Spirit also brings with it the SystemRDL specification, a language for defining registers in an SoC, which has a close fit with IP-Xact. This started life at Denali, which then donated the specification to Spirit. The other main standard that Spirit hosts is the IP Tagging format that it inherited from the ashes of VSIA. Von Vignau pointed out that, long before there were any thoughts of merging with Accellera, Spirit considered a merger with VSIA. However, VSIA decided to dissolve before any negotiations began.

The open question is how far consolidation of standards bodies can and will go in design automation. The Silicon Integration Initiative (Si2) and OCP-IP are possible candidates for merger. A merger between Accellera and Si2 would be a lot more complicated but would help solve the lingering problem of having two competing and not very different formats for co-ordinating low-power design.

OCP-IP, which kicked off as the host for an IP interconnect standard, has been working on a variety of IP-focused initiatives that can dovetail with Spirit's own efforts quite neatly.

Mehta and von Vignau said Accellera and Spirit have quite enough on their plate right now before anyone can think about any further merger. "The full focus is on this merger and at this point there are no other thoughts in our minds," said von Vignau.

But, this is a period when people don't want to think about dealing with too many different organisations, standards or policies. "The times are inviting consolidation with the industry," said von Vignau.