At first glance, the 40nm process presented by Toshiba at IEDM last week looks no great shakes. In a session dominated by 32nm processes, this one seemed not just one generation behind but a bit more than that if you compared its headline figures with the 45nm technologies described by Intel and TSMC in 2007. But a closer inspection reveals a process with a bit more going for it.
When Toshiba says it's a 40nm, the company means the gate measures 40nm. This is a good 30 per cent longer than the minimum gate length quoted by Intel and TSMC last year and puts the transistor more in line with a 65nm or 55nm process – actual gate length has outpaced the notional length contained in each node's title for some years. As a result, figures such as current drive, which control the performance of the core transistors, are lower than those quoted by TSMC. The NMOS transistor of Toshiba's high-speed version of the process has a current drive of 840µA/µm, around 30 per cent worse than the process that turned into TSMC's own shot at a 40nm technology.
But, if you compare with a 65nm process, where transistors often wind up in the 40nm-long range, Toshiba's numbers are par for the course. The bulk technology covered by IBM and the Common Platform partners at IEDM in 2004 shows broadly similar numbers. More importantly, the leakage in the new Toshiba process is lower than in those older processes thanks to the decision to implant nitrogen atoms in the transistor channel, the use of flash-lamp annealing and just a touch of high-k in the gate over the channel, without going all the way to high-k, metal-gate structures.