Chris Edwards: April 2008 Archives

Late yesterday, Forbes reported that Apple has decided to buy boutique chipmaker PA Semi. So, the conference call later today where Apple announces its results for the second quarter of 2008 is going to be interesting. And there will be a bunch of silicon suppliers wondering what's going wrong for them.

Discarding the possibility that Apple has decided the move to Intel, and its rejection of PA's PowerPC processor in 2006, has been an awful mistake and it suddenly needs to press the architecture reset button, the move by Apple suggests that the company is not all that happy with the shape of today's integrated circuit (IC) business.

One possibility is that Apple has decided it needs more in-house chip designers and buying PA was a quick way to staff up. That's not unusual in this business: it's a surprisingly common way of getting hold of people who can design the analogue circuits that most electronics engineers fear to touch. Even after you've bought in a bunch of processors and memory, there are other places a computer maker can use experienced IC designers to get an edge on its competitors. You don't see that much in the PC business but it's a lot more common in places like the phone market.

Reporting from TSMC's technology symposium in California this week, Mark LaPedus of EETimes reports that the foundry is planning to introduce a high-k/metal-gate option with its 32nm process. However, it will be aimed at higher-performance designs: the low-power process, which is likely to be the mainstream option, will remain based on a conventional polysilicon gate. It's worth noting that TSMC considered high-k and metal gates for its 45nm process as an option, then opted to concentrated on a polysilicon gate. On the 32nm process, the metal gate will let TSMC get faster transistors without pushing leakage current through the roof. There are very few details on what TSMC is doing, but it seems likely that it will be a single-metal process - and probably not the same as IBM's take on this technology. A joint research project between NXP Semiconductors and TSMC based at the IMEC research centre in Belgium has been working on an approach that uses dysprosium oxide to act as a dielectric and a way of tuning a single metal, such as titanium, to work with the two types of gate needed on a CMOS process. There is no news on when the higher-performance process might arrive. Based on the experience with previous nodes, it is likely to be later than the low-power version.

There was a telling moment in the conference call hosted by Altera ostensibly to talk about its 1Q08 results but also drop in a few hints about an upcoming family of programmable logic chips.

Historically, Altera and market leader Xilinx have taken lumps out of each other as they vied to be first onto each manufacturing process. But something changed at the 65nm process node. Xilinx was quick to get its high-end parts out on the 65nm technology, but nowhere near as quick as the company's claims over having first silicon on that process. Altera was behind but took the opposite tack: putting its cheaper Cyclones onto TSMC's 65nm process first. Then it all went quiet. The launch of the 45nm process went off with both Altera and Xilinx being uncharacteristically quiet. It began to look as though a kind of chip that had become the foundries' banker for early silicon had suddenly fallen off Moore's Law.

It seems that the programmable-logic makers are still in the running, just not as quick to jump on a new process as they used to be. And it seems that Altera wasn't aware just how advanced its next process would be until TSMC decided it would lop another 5nm off - in name at least.

Sometimes, small deals can wind up changing the shape of a market. The deal between Blaze DFM and TSMC that has been gestating for close to a year is possibly one of them: it recalls the giant leap of faith that Artisan took when it came up with the "free library" idea.

Basically, Blaze and TSMC have cut a deal that will see the Taiwanese foundry use a version of the Blaze MO tool to alter transistors in a layout to make them less leaky just prior to manufacturing. The idea is not new and fairly simple: you make the transistor gate longer on logic paths that don't need to be fast. This typically shifts the threshold voltage up, which cuts leakage. STMicroelectronics has been offering the same sort of modifications using different logic cells. What is different is the nature of the deal between Blaze and TSMC and what it could mean for the whole DFM business.

Instead of trying to sell tools on a per-seat basis for something like a couple of hundred thousand dollars – the regular EDA business model – TSMC will host the tool. Although the companies will not talk about the money side of the deal, it does look broadly similar to the Artisan free-library model, where the foundry paid a royalty to Artisan for each chip made and charged a bit more for each chip to the customer.

For Jacob Jacobsson, CEO of Blaze DFM, this approach, in a way, opens up money that isn't available to the EDA tools vendors. "EDA has a had a more or less stagnant $3bn budget for as long as we can remember. It is more attractive for us to align with the manufacturing side of the business."

There is some more detail available on the Common Platform alliance 32nm from the advance material put together by the organisers of the VLSI Technology Symposium. It illustrates the kind of bets that the fabs and foundries are making on the next generation of silicon, although the details are still sketchy.

With the 32nm generation, IBM and its partners expect to be able to deliver a process that exceeds the industry consensus on what is needed at that point. The consensus is summed up in the pile of documents that go by the name of the International Technology Roadmap for Semiconductors (ITRS). Taken together, the documents are effectively the guidelines for what the industry needs to stay on Moore's Law.

Scattered throughout the PDFs are tables of specifications that semiconductors should get close to if they are to be useful at a given process geometry. The numbers are all colour coded: yellow means tricky but possible; red means nobody has an answer yet, or at least one they've shared in public.

Earlier today, IBM put out a release claiming a major "performance leap" for chips that use its forthcoming 32nm semiconductor process. Working out what's changed since the last release is a bit trickier. Basically, IBM and some of the companies in its group of chipmaking collaborators have made a bunch of test chips and are now confident enough to declare the 32nm process open for business.

Other than that, the content of today's missive is not broadly different from the one that IBM and its partners put out just ahead of the chipmaking industry's big conference on process technologies, the International Electron Device Meeting in Washington DC, held late last year. There really isn't a lot more detail, other than there is now a timetable: IBM will start running prototypes for customers of the companies in its Common Platform alliance in the third quarter of this year. The implication is that the company's in the Common Platform team will have a working 32nm process in the second half of 2009, about the same time as Intel and TSMC as long as they stay on schedule.

Writing for EETimes, Bolaji Ojo makes a fair point about the wireless deal between STMicroelectronics and NXP Semiconductors deal: it's not a pooling or a merger. It's a purchase. NXP just happens to hold a small share of NewCo for the moment.

That ST sees it as a purchase was made clear in the second conference call that ST held after the call it hosted jointly with NXP's Frans van Houten. On the first call, where everybody was really happy to be working together, van Houten wanted to point out that the Dutch-American chipmaker was in NewCo for the long haul, albeit with a 20 per cent share of the new company. That combination of option calls described in the release was just a formalisation of a possible exit, just in case.

Carlo Ferro, chief financial officer of ST, made the position much clearer on the second, NXP-less call. "It is evident that ST starts with a 80 per cent and has identified a possible opportunity for a further move. ST has granted a call option after three years and NXP has a put option. The future exit cost will significantly depend on the future financial performance of the company."

Now here's the important bit: "ST is prepared for any possible evolution but we exclude the possibility to separate the business [from ST]. And we are prepared through the exit formula to consolidate the business."

Later on, Ferro added, when talking about the effect of the options on ST's financial performance, which he claimed should more or less cancel each other out on the balance sheet: "It is an opportunity to eventually buy the business at predefined terms."

John Busco at John's Semi-Blog has pointed to the launch by Nascentric of an analogue-circuit simulator accelerated by nVidia's graphics processors, and wondered: "Will general-purpose GPU computing become the acceleration platform for EDA?"

I was sitting at the Many-core and Reconfigurable Supercomputing (MRSC) conference in Belfast the other week wondering the same thing. In recent years, hardware-specific EDA has been a dirty word. Mentor Graphics, which made its name selling proprietary workstations before it became a software-only company made a foray back into hardware in a deal with Mercury Computer Systems in late 2006. Mercury used the IBM Cell processor – the same one used in the Sony Playstation 3 – to speed up the job of checking chip designs before they go to fab. Mercury sells the hardware and Mentor provides a special version of Calibre.

It's not clear how well hardware acceleration has gone for Mentor and Mercury. However, in its 2007 annual report, Mercury declared that it saw a "slight rebound" in its semiconductor business, partly due to the sale of one accelerator for chip-mask inspection – which is not related to Calibre – and its deal with Mentor. The number-three EDA company has been busy showing off the hardware at events like the SPIE lithography conference, so the company must have some faith in the idea of speciality accelerators.

The way IBM describes its racetrack memory – yet another candidate for "memory of the future" – it's easy to be left with the impression that Big Blue is out on its own with this one. Stacey Higginbotham breathlessly opines: "IBM sure has some seriously crazy semiconductor researchers locked in its basement. These guys question everything when it comes to advancing chip technology."

Maybe IBM does. But it's not alone. What IBM claimed in the press release was that a memory 100 times denser than today's flash devices is on its way:

"The devices would not only store vastly more information in the same space, but also require much less power and generate much less heat, and be practically unbreakable; the result: massive amounts of personal storage that could run on a single battery for weeks at a time and last for decades."

Sounds great. When can I buy one? Not any time soon if you look more closely at what IBM's release is based on. The journal Science has published a paper on the work of Stuart Parkin's group at its Almaden lab in San Jose that describes a tweak to a type of magnetic memory. It's a bit like a solid-state disk state. You store bits magnetically: the state depends on which way the stored field points, either forwards or backwards along a metal wire.

When former STMicroelectronics R&D director Jo Borel tried to convince the French government that it should try to convince Europe's three largest chipmakers to merge, he almost certainly didn't have in mind what ST and NXP Semiconductors plan to do. They are not merging the entire companies but taking the wireless business units and glueing them together.

The argument used for the merger is not all that dissimilar to Borel's: it's all about scale. Borel wanted Infineon, NXP and ST to team up to be big enough to build and operate a leading-edge fab - it is something that is only worth doing if you are selling billions of dollars' worth of chips every year out of that facility. Not able to do that on their own, the three companies expect to buy wafers made using the latest processors from foundries such as TSMC.

The availability of foundry-made silicon is one reason why Infineon chief Wolfgang Ziebart has said that there is not all that much point in trying to be big for the sake of being able to keep building fabs. His view is that companies will specialise and do whatever they can to be in the top three of their chosen market. Infineon has been bulking up in wireless recently, thanks to its purchase of a business unit that was only briefly part of LSI when that company bought Agere Systems.

The move by NXP and ST is on a larger scale, creating an as-yet unnamed joint venture that is comfortably in the top-three wireless silicon makers and around twice as big as the next largest supplier. According to iSuppli, that will be Infineon once the deal is done. The German company is at the head of a line of $500m to $1bn suppliers. The ranking switches a little if you look at it from the perspective of baseband processors - the single most important segment in cellular wireless silicon. ST lies at number three, NXP at five.