Shrinking Violence Blog

Racing for the MEMS stack

2010-07-05T20:18:21Z

Just ahead of Apple’s launch of the iPhone 4, Carmelo Papa, general manager of STMicroelectronics’ industrial and multisegment sector, was bullish about a new market for the company. He declared that this year would be the dawn of the ‘era of the gyroscope’.

A few days later, Apple CEO Steve Jobs was demonstrating what the combination of an accelerometer and three-axis gyroscope could do in a mobile handset. ST made its own video for the company’s Field Trip, a series of presentations to financial analysts, to show how the gyro and accelerometer combination could be used to navigate through the streets of Venice - using dead reckoning where the signals from GPS satellites cannot be easily seen in narrow streets.

As ST is the only vendor claiming to make an integrated three-axis gyroscope, this is the one that is suspected to be inside the iPhone 4. Teardown experts such as Chipworks and TechInsights believe die markings confirm ST as the manufacturer.

Benedetto Vigna, head of ST’s MEMS division, claimed that the market for gyros in consumer will be three times bigger than that for similar sensors in automotive – where they are more widely used today for stabilisation control – by 2014.

Although the initial demonstrations revolve around games, Vigna said dead-reckoning calculations can make it possible to pinpoint a user’s location inside buildings such as shops and museums, narrowing location-based information to a rack of clothes or a museum exhibit.

Although it does not need all three axes, optical image stabilisation is another use for cameras and phones. Papa said applications for the MEMS gyro can go further, including vibration control in washing machines. “The potential market is huge,” he said.

According to Benedetto Vigna, the decision to make a three-axis gyro was taken quite late in the day in an indication of how integration and fast turnaround are becoming crucial in getting MEMS into high-volume consumer designs. “By the end of last year, we understood that the market was willing to move faster,” said, explaining that the company had been working on a two-axis design.

“On the 21st October, we put the first transistors on the layout. And you are now holding the product,” he said as he handed out tiny 4x4mm packages. “Because of the nimbleness of the team we now have a three-axis gyroscope.”

]]> ST’s aim is to integrate the gyro and accelerometer and other sensors together with analogue processing using a stack of chips. The MEMS can potentially all go on the same die, with the analogue and ultimately microcontroller going underneath in a multichip package.

In contrast to ST, Freescale is in no hurry to develop consumer-level gyroscopes. ST’s Papa claimed his company will see $100m in revenue from its gyroscope MEMS products by the end of this year, with practically zero in sales at the start of this year. Gervais-Ducouret conceded a few million gyroscopes will sell this year but is not expecting such as quick take-off. Freescale is looking to 2012 as the time “we think there will be a booming in terms of the market for gyroscopes,” he added.

“We have been focusing so far on gyroscopes for automotive,” said Stéphane Gervais-Ducouret, director of global marketing for sensors in the consumer market segment of Freescale, adding that power consumption is an issue for this kind of sensor.

Typically, automotive-grade gyroscopes consume more than 10mA per channel but have the benefit of running from a bigger power source. “If you look at the mobile phone, you are looking for less than 1mA,” he said. ST’s current gyro consumes around 2mA per channel.

Where Freescale has put its effort is into integration. “[ST’s offering] is not integrated all in one. It is not integrated to this level,” said Gervais-Ducouret, referring to the inclusion of a microcontroller in the package along with the MEMS-based sensors and analogue conditioning electronics. “The only thing not on the same piece of silicon are the MEMS-based sensors.”

By moving sensor processing into a local microcontroller, Gervais-Ducouret said it’s possible to achieve power savings compared to running those same algorithms on a host applications processor. “It offers customisable power management – you can change the sampling frequency and have auto wakeup and auto-sleep.”

By moving the processing to a dedicated microcontroller, it’s possible to watch for wakeup gestures without forcing the more power-hungry applications processor to run. This can be extended to applications such as pedometers that use readings from the accelerometers to count steps. “It can run all day without waking up the whole phone,” he claimed.

For the first product, which incorporates accelerometers, Freescale has developed a number of packaged routines that will detect different types of user interaction. The idea is that the company can provide these as canned functions that handset and gadget makers can more easily roll into their designs.

Although the two companies see single-package motion and position detectors as the end-point, the companies are starting from different points.

No more shopping for Virage as Synopsys becomes the customer

2010-06-10T15:01:57Z

After going through an acquisition spree of its own, Virage Logic has agreed to be bought by EDA company Synopsys for about $315m in cash. The move follows only a month after Cadence Design Systems’ announcement of its plan to buy memory-IP specialist Denali.

The rationale from Aart de Geus, CEO of Synopsys, in the conference call for the purchase is not all that different from Cadence’s. “Putting together these IP blocks and making sure they work together is essential,” he said.

Like Cadence, Synopsys is expecting an increase in the use of third-party IP by chipmakers. “The trend of IP outsourcing is a massive trend. People are moving towards using commercial IP where they can except where they can add differentiation,” de Geus said, adding that a growing number of companies are realising what they thought was differentiated home-grown IP could be just a millstone. “What companies produce is not necessarily differentiated. Some of the standards they need to work with are so complex, their own people can’t necessarily do a cost-efficient job there. The downturn has helped many executives realise that outsourcing these efforts makes a lot of sense.”

De Geus argued that very little of the IP produced by Virage overlaps with that created at Synopsys. The EDA company backed away from the acquisition of memory-IP specialist Mosys in 2004 and has not developed its own. Even earlier, a move into standard-cell IP through the acquisition of Silicon Architects in the mid-1990s ended when Synopsys wound up the operation. De Geus explained that the move was “premature” and that it had gone into the business before it had a place-and-route tool (later acquired through its 2002 purchase of Avant) that would make use of those cells.

Virage’s roots lie in low-level IP such as memory cores and standard cells but has, more recently, moved into larger cores through the acquisition of ARC International and NXP Semiconductors’ IP design group. Potentially, the addition of the Virage line-up brings Synopsys into conflict with ARM, with which Synopsys developed the verification reuse and low-power design methodologies.

De Geus argued that the processors from ARC complement those of ARM, agreeing with one analyst’s use of the term ‘ancillary’ to describe them. “ARM is one of our most important partners and is a friend of the company, a company around which we have built a number of our offerings. ARC is interesting because it so supports the ARM core processor. It provides a controller that can be used for subtasks to offload the main processor. It will be interesting to see how we can build solutions with ARM.”

ARM has gradually backed away from areas that Synopsys has moved into in the IP space. The ARM Primexsys portfolio of peripherals failed to take off but Synopsys’s main successes in IP lie in this area. Although ARM has tried to get into digital signal processing (DSP), it is another area that the UK company has discontinued its effort, choosing to focus on graphics instead. ARC has, in contrast, focused heavily on audio and similar DSP-based products.

Where ARM and Synopsys will compete head-on is in standard-cell libraries and it’s a business where ARM has spent heavily to keep up with process technology. Having Virage provides Synopsys with a way to align design-implementation tools with the cell libraries, something that is becoming more important as design rules get ever more restrictive. Will ARM engineers get the same access to the Synopsys tools people post-acquisition?

Forget petascale, here comes the exascale supercomputer

2010-06-08T16:17:48Z

Belgium-based research institute IMEC has teamed up with Intel and a group of local universities on a programme that is intended to pave the way for exascale computers – supercomputers that are close to a thousand times more powerful than those being commissioned today.

“In 1997, we saw the first terascale machines. A few years ago, petascale appeared. We will hit exascale in around 2018,” said Wilfried Verachtert, high-performance computing project manager at IMEC, explaining that these machines will be able to perform 10¹⁸ floating-point calculations per second.

The most powerful supercomputer being made today is the Cray XT5 Jaguar with a rated performance of close to 2 petaflops

At a presentation held to celebrate the opening of a new cleanroom at IMEC and the foundation of the ExaScience lab, Martin Curley, senior principal engineer and director of Intel Labs Europe, said: “We are focused on creating the future of supercomputing. We have a job to do of creating a sustainable future. Exascale computing can really change our world.”

Curley said a the two main problems will be power consumption and the difficulty of writing highly parallel software. The performance required is the equivalent of 50 million laptops which would demand thousands of megawatts of power.

He explained that, by the time exascale computers are likely to appear, silicon-chip geometries will have dropped to 10nm. Although these devices can potentially run at tens of gigahertz, Curley said power consumption concerns would force supercomputer makers to run them much more slowly and potentially even slower than today’s processors. The move will demand billions of processing units in one supercomputer. “How are we going to achieve that? The only way is through billion-operation parallelism.”

Curley added: “Even with just 10 to 12 cores, we see the performance of commercial microprocessors begin to degrade. The biggest single challenge is parallelism.”

The ExaScience lab will, as its test application, work on software to predict the damage caused by the powerful magnetic fields that follow solar flares in the hope of providing more accurate information to satellite operators and the power-grid companies.

With current-generation supercomputers, the mesh used to analyse field strength has elements that are a million kilometres across, far larger than the Earth itself. An exascale machine would make it possible to scale the mesh size down to elements that are 10,000km across.

Verachtert said the project aims to get the power consumption of a machine from 7000MW – based on today’s technology - to 50MW, “and that is still higher than we want”.

One problem with a supercomputer than contains millions of discrete processors, each one containing thousands of processing elements, is the expected failure rate. “My optimistic projection is that there will be a failure every minute. It’s possible that there will be a failure every second. We have to do something about that.”

The failure rate will have a knock-on effect on programming. Today, it is possible to break up applications so that portions can be re-run after a hardware failure, which may happen once a day. That is impossible as the size of the machine scales up. Verachtert said the methods programmers use will have to take account of processors failing, using checkpoints and other techniques such as transactional memory – which Intel has researched heavily already – to allow code to be re-run automatically without disrupting other parts of the application.

Linaro scratches the chipmakers' software itch

2010-06-04T20:39:16Z

You’d think people would be bored with forming embedded Linux consortia by now. But the creation of Linaro demonstrates that there was least one unfilled niche.

Set up by ARM and a bunch of chipmakers, Linaro is different to some of the others that have appeared over the past few years, which are mainly intended to provide ready-made environments for mobile phones and internet tablets.

All of these groups run the risk of being home to nothing more than tumbleweed. A bundle of source code gets dumped in shortly after creation but interest wanes as developers concentrate on the major platforms - right now that’s likely to be Android.

At first sight, Linaro does not look too interesting to developers working with Android and its analogues. But that probably won’t affect Linaro’s success because this group scratches an itch that the chipmakers themselves have, which is the massive cost of developing low-level software for their applications processors. Since the late 1990s, as I describe in this feature for Engineering & Technology, the chipmakers have been bundling more and more software with their devices. But they haven’t picked up any more cash for their efforts.

Instead of doing all the work individually, and spend loads of money, they can club together. Most of them are ARM-based and they have broadly similar system architectures, although things such as the graphics accelerators will differ substantially. Amortising the cost of the support software for environments such as Android and WebOS is not going to solve the chipmakers’ software problems overnight - there are other platforms they need to support - but more cooperation at this level can put a dent in the heavy cost of development.

ARM has already kicked off a similar endeavour for its Cortex-M microcontrollers, although it operates differently to the open-source consortia. The Cortex Microcontroller Software Interface Standard (CMSIS) is designed to support a library of functions that users can bolt into their embedded controllers and has the backing of Cortex-M licensees such as NXP Semiconductor and STMicroelectronics. You can view Linaro as an extension of that kind of effort but with a different target: the Cortex-A series and mobile terminals.

It will be interesting to see if other independent developers turn up and contribute but that may not matter as these are companies with a ton of developers now who have customers who want to base their systems around at least one of the higher-level Linux platforms.

ST's ramp-up to 20nm

2010-06-03T11:24:41Z

STMicroelectronics expects to put its first 20nm process into production at its Crolles fab in France by the end of 2012 after completing a programme to catch up on internally produced processes with the major foundry suppliers.

Although the company expects to increase the amount of production that it outsources to foundry from its current level of 15 per cent to 20 per cent long-term, ST decided recently to put more investment into Crolles in a bid to quickly move to parity with the processes supplied by the major foundries and to be able to build its own derivative processes, such as the recently announced 32LPH process which uses a high-k metal-gate transistor structure.

Jean-Marc Chery, CTO of ST told analysts at the company’s annual Field Trip: “I am confident we will be able to to tape out in our 20nm low-power process the first product by Q4, 2012. This will gain more 30 per cent performance and a 2x shrink factor [over the previous process technology].”

Chery said the company is prototyping with its 32nm process and expects delivery of its first production immersion scanner next week so that production can ramp up in the third quarter of next year. This process ramp will follow just one quarter after the ramp for its low-power 40nm process. The 45nm process will ramp up in the fourth quarter of this year.

Globalfoundries' turn in tit-for-tat expansion plans

2010-06-01T08:21:00Z

The people from GlobalFoundries travelled to Taiwan to let number-one foundry TSMC know that the youngest foundry is ready to keep on spending in what has become a capacity war in that business. It follows soon after TSMC’s own decision to push harder on capacity expansion with the building of its own Fab 15.

Although all this expansion might look like a one-way bet in the current market conditions, where you can pretty much sell everything you can make, by the time all of this capacity is meant to come onstream it could well be a different story.

Already trying to fill the second phase of its fab in Dresden as fast as possible with chipmaking gear, GlobalFoundries said at the Computex trade show in Taipei that it will build another section - once grants from Germany turn up - over the next two years. This will add 20,000 wafers per month, increasing Dresden’s capacity by one-third when that expansion has finished. Given that they have not started building the extension yet, this is a very aggressive schedule for filling a fab.

However, the schedule for the Malta, New York fab has slipped slightly. Originally slated to go into volume production in 2012, this is now not expected to happen until 2013. By the end of 2012, it will just be pilot production. However, Malta does not miss out on the capacity splurge. Fab 8’s peak capacity moves up from 42,000 wafers per month to 60,000 - eventually. Based on previous estimates from GlobalFoundries, this is unlikely to happen before the end of 2015.

Pushing the volume ramp at Malta back a bit may, if current market projections prove correct from analysts such as Future Horizons and IC Insights, help GlobalFoundries avoid walking straight into a capacity glut in 2012, and still capitalise on a recovery in 2013. However, things rarely work out that neatly in this business.

There’s more. GlobalFoundries’ owner ATIC said it would build a 3km² ‘technology cluster’ in its home of Abu Dhabi. There is no firm news of a fab being built there other than strong hints: “GlobalFoundries is committed to partnering with ATIC to share best practices and expertise in cluster creation in the near-term and putting a significant technology and manufacturing presence in the region long-term.”

IP's a slow burner

2010-05-21T10:18:20Z

Cadence Design Systems has decided that semiconductor intellectual property (IP) is important to the chip design and so has bet fairly big on its $300m cash acquisition of Denali together with a plan to pre-integrate IP from other suppliers.

Let’s have a look at the rationale. Design costs keep going up - in proportion to the number of gates you can squeeze onto an integrated circuit (IC).

“The only thing that scales is IP. You can’t move to the stratosphere in terms of abstraction. You have to use IP…The SoC battle is won or lost over the quality of IP…IP reuse will go up to and beyond 90 per cent of the die. But having multiple IP vendors for one chip design brings challenges, so you will qualify IP vendors rather than individual IP cores. Everything points to consolidation.”

Oh no, wait. That wasn’t Cadence. Those were the words of Raul Camposano in mid-2004, who was then Synopsys CTO. Sounds a lot like the Cadence rationale doesn’t it? But it doesn’t say a lot for Cadence’s new found strategy rewriting the rules of EDA. It’s easy to see how an EDA-plus-IP strategy can develop because you only have to look at what has happened at Synopsys, the only major EDA vendor so far to have made a living at IP. Mentor Graphics had a go but that did not turn out so well and the company got out of the business.

Since the Internet bubble, the share of Synopsys’s revenues from IP has hovered around 6 to 8 per cent according to a succession of 10K annual-report filings. The share was as high as 10 per cent in 2001 but this was before the company acquired Avant, when the IP share slid to 5 per cent.

Synopsys’s 2003 revenues totalled $1.2bn. In 2009, they came to $1.4bn. IP revenues averaged about 7 per cent of the total in 2003, providing Synopsys with $84m just before Camposano made his prediction about the rise of IP. Now, they amount to $140m. That’s about 9 per cent per year, about the same as the semiconductor industry’s long-term average growth. It’s not transformative growth by any means. This wasn’t because Camposano was wrong - far from it - just that the increased use of IP does not necessarily translate into massive sales.

As chip capacity increases - which pulls in more third-party IP - design starts go down, slowing down the growth of the IP suppliers. You could argue that maybe Cadence has entered the market at just the right time. But it takes time to establish a reputation as a stable, reliable IP supplier as Synopsys chairman and CEO Aart de Geus pointed out in the company’s most recent results conference call. Buying Denali gives Cadence greater credibility in the market than simply bootstrapping its own operation but it will take time for the company to see a return on its $300m, if it sticks at it.

Infineon drops Elpida case

2010-05-20T13:20:23Z

Infineon Technologies has decided to drop its complaint against memory maker Elpida in what looks to be a case of patent stalemate.

The German company decided to go to the US International Trade Commission in February, claiming that Elpida had infringed some of its patents. As Infineon backed out of the memory business with the closure of Qimonda, it looked as though the German chipmaker aimed to claw back some cash by finding infringers of memory-related patents. It has wound up with a patent cross-licence which, although is not to be sniffed at, doesn’t sound like a wholesale victory.

To get the money rather than the cross-licence from patenting it’s important not to be actually making stuff (and so it’s just as well that most semiconductor patents are in the hands of companies making stuff otherwise the whole industry would grind to a halt).

Cadence tries to avoid the Tality trap

2010-05-10T08:47:08Z

When Cadence Design Systems said last week it was getting back into the business of supplying intellectual property (IP), my first reaction was: “Oh look, they’ve reinvented Tality.” I wasn’t alone. Just about everyone who I talked to afterwards before and during the International Electronics Forum in Dresden said more or less the same thing: “It’s Tality all over again.”

Back in the late 1990s, as startups rushed to get chips into the market and cash out with an initial public offering (IPO), the Tality subsidiary seemed to Cadence a good way to get more money out of the design business. Tality was to be a ‘design factory’ for chips. You came in with an idea, Tality - for a fee - provided you with the chip design that you could then get fabbed at a foundry.

There was only one problem: Tality lost money on the deal. It could never charge enough to cover its costs and, eventually, the whole operation was wound up or sold off in bits.

One part of the Tality plan was to develop commonly used blocks of IP and use it across different projects, with the advantage that the engineers knew how to tie it together. Fast-forward ten years and you have a broadly new management team in at Cadence trying to work out how it expand its business without having to commit to the expensive R&D needed for deep sub-micron chip-design tools.

Having realised that making lumps of IP work together is not often straightforward, the team came up with the idea of doing a lot of that integration work for the customer. Other than the name, it sounds as though a part of Tality rides again.

]]> Vishal Kapoor, vice president of product management at Cadence and responsible for the new IP operation, said at the launch in Germany: “We don’t want to be Tality and do all the design services for you. We want to provide integration-ready components. The services we provide are in support rather than a replacement for design.”

To prevent the service element from spiralling out of control, the customer’s ability to edit the IP will be restricted. “The methodology is constraining: we have optimised it for you. Thou shalt not touch. But, to take that ability to modify away from customers, you have to give them something else. So we assure them compliance,” said Kapoor.

Cadence will start with common protocols such as USB and provide everything from the controller to the physical-layer transceiver. To avoid having to build a complete IP-design team in the way that Synopsys has - and which has built up a bundle of protocol-IP already in the past ten years - Cadence is licensing IP cores themselves from other players, such as IBM, RapidBridge, GDA and Sonics. What the Cadence team then does is bolt the pieces together, make sure they play nicely together and provide that as one chunk of logic and software.

Ultimately, if the first phase goes according to plan, Cadence will assemble these stacks into combos on the basis that where you find USB, you also find networking interfaces and memory controllers.

If you’re thinking this concept of providing pre-integrated IP is familiar, the overall concept is not far from what ARM tried to do with Primexsys in the first half of the past decade. Bits of this still exist but the UK processor designer gave up on trying to develop entire platform definitions under the Primexsys brand after the company discovered it was trying to push water uphill with its offering.

The desire to customise IP to suit a particular SoC’s bus structure is Cadence’s biggest headache. But, with millions more transistors now available to chipmakers compared with five or ten years ago, the desire to mess around with a titchy little USB controller has to be waning, even if it’s taking years for engineering teams to look at IP more as a black box.

Kapoor is under no illusions as to how chipmakers want to buy IP. “The market is moving away from IP-based royalties,” he said.

By sub-licensing IP, Cadence is constrained by the terms of its suppliers but the understanding that chipmakers, although they may tolerate royalty payments for ARM processors and specialised cores, they are not going to pay a few cents for each protocol controller they put on-chip. An upfront licence fee is quite enough, thank you. This arrangement is somewhat more difficult for a company such as ARM to swallow than it is to Cadence, which is used to licences, subscriptions and maintenance deals.

A further constraint on Cadence is on who fixes the bugs in the cores themselves. Those fixes need to be done by the supplier rather than Cadence. In principle, this should not be a problem but, with many of the bugs that now turn up in integration tests, determining fault is not always easy and could lengthen the process of getting working IP combos out of the door.

When talking about its IP plan, and implicitly pointing to Synopsys as the other major player, Cadence likes to call its approach to IP provision “open”. This openness is largely based on the fact that Cadence is not writing its own RTL rather than any grand plan to go open source.

However, Cadence aims to provide a way for IP suppliers not on the initial list to get onboard by qualifying their own cores through the same process used by the company’s integration team. This will help Cadence scale up the operation, Kapoor said.

“Once the qualification criteria are established, we will offer those criteria to third parties to qualify against and sell,” Kapoor added.

If the company pulls this one off, it might provide a de facto alternative to what the IP industry currently has for estimating the quality of an individual IP core. Right now, that’s a self-certification spreadsheet that evokes little more than wry laughter around the industry whenever someone mentions the possibility of a revived IP quality standard. A published qualification process could help the wider industry.

Update: Cadence is going to do a bit more of its own design with the $315m acquisition of memory IP specialist Denali, and in real money too, not shares.

TSMC to start work on Fab 15

2010-04-27T15:44:48Z

TSMC is to break ground on its third major 300mm (12in) fab in the middle of this year, the company said as it released slightly better than expected results for the first quarter of 2010. With the existing 300mm plants, Fab 12 and Fab 14, nearing their planned maximum capacity of 100 000 wafers per month, it’s time for a new one.

As it will take at least a year to build the shell, Fab 15 - which was originally earmarked for Tainan rather than its revised location of Taichung, roughly midway between TSMC HQ in Hsinchu and Tainan, before the chip market imploded in 2001 - will not play much of a role in TSMC’s production before 2012.

When it gets going, chairman and CEO Morris Chang, said Fab 15 will support capacity expansion for the 40nm process and will add 28nm before moving onto the 20nm technology and beyond.

In the meantime, TSMC is rushing to get more equipment into Fab 12 and Fab 14, pushing 300mm production up by 35 per cent by the end of the year. However, Chang said these fabs are nearing their planned maximum capacity of 100 000 wafers per month. The company plans to use the majority of its capital expenditure for 2010 in the first half of the year to ensure much of the extra capacity is in place by the end of 2010.

Older 200mm fabs are not to be left out of the expansion - Shanghai, in particular will see new equipment for the “more than Moore” programme the company adopted to keep its older fabs running.

TSMC saw a modest rise in sales from the fourth quarter of last year to the first quarter of 2010 rather than the expected post-Christmas dip.

CFO Lora Ho said: “Contrary to expectations, first quarter revenues and wafer shipments slightly increased.” The growth was driven by communications and consumer products, coupled with stronger demand on the recently introduced 40nm process, helped by improving yields.

Chang said yields on the 40nm are now as good or better than those encountered on the previous 65nm process at the same stage of its development. In the first quarter, the foundry sold $411m worth of wafers to customers made using the 40nm process – revenues from the 65nm process passed the $400m point two years ago.

“Combined revenue from 40nm and 65nm processes accounted for 41 per cent of total wafer sales,” said Ho.

Phase-change memories get real

2010-04-21T15:46:56Z

Phase-change memory (PCM) has been gestating for close to 40 years but Numonyx has come up with devices that can begin to take on NOR flash in embedded systems designs. By the end of the year, the company reckons it will have ready denser devices that will suit mobile-phone makers.

Numonyx has pushed the write endurance of 128Mbit phase-change memory (PCM) devices to the point where it is now ten times that of typical flash memories and has launched a family of parts to replace DRAM and flash in embedded systems. The company is now working on higher-capacity memories to go into future cellphone designs, agreeing to use the same interface as competitor Samsung.

Giuseppe Crisenza, vice president of strategic alliances for Numonyx, said the company has been optimising the technology on a 90nm process since it launched the first memories in late 2008. In that time, the write endurance increased from 100,000 to 1 million cycles.

Because flash memories have lower cycle counts they need to use techniques such as wear levelling to prevent overused bits rendering the devices useless. PCM devices have the further advantage of allowing individual bits to be written unlike flash memories that have to be erased in blocks and rewritten.

Numonyx will sell both serial- and parallel-interface versions of the 128Mbit PCM, aiming mainly at the general embedded market rather than the mobile-phone business, although Crisenza said there are low-end mobile phones for the Asian market that could use the devices.

“There are a lot of applications that for cost reasons prefer the serial interface,” said Crisenza.

]]> The SPI-based serial device will be able to function more like a traditional EEPROM memory, which only scaled up to densities of around 1Mbit, with flash used for higher capacities. Although the devices will cost more than equivalent size flash memories, Crisenza said the overall system cost can come down because one PCM can replace a DRAM and NOR flash memory array in many embedded systems, perhaps sitting alongside a NAND flash for bulk data storage. The idea of PCM being a do-it-all memory has gone away.

“There will not be a universal memory,” said Crisenza. “PCM can play between DRAM and NOR to reduce the overall cost, even if the device itself costs a little more. Very often, embedded device designers are looking for small DRAMs that aren’t available anymore or are costly devices so they have to use embedded DRAM. With this kind of device we can replace the embedded DRAM, E² and code flash.”

As devices scale, Crisenza said the write endurance is likely to improve and that the manufacturing learning curve should also push the cycle count higher.

“When we come out with 1 or 2Gbit devices, there is no way to go serial. They will be parallel, high-speed interfaces,” said Crisenza.

“To speed up development we are jumping from 90nm to 45nm. Our goal is to provide samples of 1Gb at the end of this year to the main customers in wireless,” Crisenza added. “There will be two main devices, one that is a NOR replacement and the other will have a DDR2 interface. The specifications for this second one have been agreed with Samsung. Using a common specification will encourage customers to go with this solution.”

Cheap tricks for plastic circuits

2010-04-14T17:37:08Z

Two years ago, the hot topic at Printed Electronics in Dresden was colour displays. But since then, Sony has beaten a hasty retreat and it’s taken longer to get to commercial monochrome printed or plastic displays than people had hoped in 2008. This year, the emphasis is on the definitely less sexy end of the business. Smart labels and packaging; low-end stuff that barely needs any circuitry at all.

Even in displays, some companies are now looking at a way to cut the cost of making existing types of screen, such as liquid-crystal display (LCDs) rather than trying to open up a market for organic LED screens, especially now that Sony has retired hurt - although Peter Harrop, chairman of IDTechEx, the company that organises the conference, reckons they will be back with updated versions at some stage.

Sharp is seriously looking at a way of using printing to replace lithography in the manufacture of its LCDs. According to Tolis Voutsas, director of the materials and devices applications lab at Sharp Laboratories of America, the company could knock 60 per cent out of the cost of making some LCDs simply by “abolishing lithography”, once printed transistors get to the necessary level of performance.

]]> Samsung chose to talk about its own work on low-cost LCDs rather than shiny, attractive OLED displays. Its 5in prototype based on organic semiconductors shows a dingy-looking image, but the development was enough to demonstrate the viability of moving from silicon to plastic transistors in the circuits that sit underneath the liquid crystal in some kinds of display.

Outside the electronics industry, the big corporations are taking note, even if they find working with such a young and understandably technology-focused industry problematic. A lot of the technologies are looking for an application, although one good sign is that companies are trying to reach out from their networks of customers and suppliers to see if someone is out there, anywhere, who can help.

Kimberly-Clark made 60 tons of its conductive paper as part of a feasibility study but came up blank in terms of products within its own portfolio that could make use of it. A reason for research scientist Tom Ales to turn up at the conference this week in Dresden was to see if someone could use a conductive paper loaded with carbon fibre in what they were doing.

The people at Kimberly-Clark had a good think about what they could do with the paper, and not necessarily the first things you think of when someone says “conductive”. For example, one of the possible applications they looked at was in heating - possibly replacing those chemically activated heat pads with something that might combine paper and a small battery or fuel cell. Being up to 30 per cent carbon fibre - beyond that level, it gets very brittle because the fibres are, as Ales pointed out, “like uncooked spaghetti” - the cPaper is conductive but not all that conductive.

Combine the heating effect with an oil or detergent soaked into the paper fraction and there is potential for something that may clean things more easily than just using the materials on their own as a lot of these things work better at a higher temperature.

Novalia’s journey into the simple got off to an early start. Formed by Kate Stone after leaving Plastic Logic, it took a sales call to trigger a drastic change in approach. She wanted to sell a company making trading-card games on the idea of using printed transistors to make them more interactive. They asked her to return in a few months to show how it might look.

“That event totally changed my perspective. It was going to take a couple of years to do that. I couldn’t do it,” she said.

The prototype she did come up with had no printed transistors in it whatsoever. “I thought, if I am going to get anything to work I am going to have to use existing technology,” she said.

In later conversations with potential customers, she has found herself lowering their expectations of what printed electronics is currently capable of.

“One company said they wanted to print RFID tags on their packaging. They had heard about printed electronics, but I had to sit them down and explain we can’t print RFID tags today,” said Stone. “But I realised that if they had conductive inks they could create a grid of lines and put a code onto the packaging. The concept was invented by thinking about what machines they had on the floor.”

To support more advanced designs such as interactive books and greeting cards, Novalia has gone back to silicon - embedding a programmable custom chip into the product that carries some sensor inputs and speaker and LED outputs. It’s not that different from the talking cards that have been on the market for some years. The main difference is in the way conventional conductive inks are used to send data to the controller.

Ultimately, some of this stuff is likely to move towards printed transistors, but only when they deliver on the promise of being cheaper and manufacturable. Even then, there’s a good chance little lumps of silicon will wind up inside many products, talking to the plastic bits. We may even see people going back and having a new look at the packaging for silicon to see if there are cheaper ways to do it so that products can be slung together in high-volume, low-tech assembly lines.

TSMC rounds down for next process move

2010-04-13T19:10:28Z

TSMC has said it will ‘skip’ the 22nm process node as its next step on from the 28nm process that is due to roll this year. However, it might just be rounding error based on past performance, as the company is aiming for a ‘20nm’ process.

This will be the third round of the Taiwanese foundry’s attempt to demonstrate that it is ahead of the process curve compared even to Intel, which went into volume production with a 32nm process at the end of last year. However, as with TSMC’s 28nm and 40nm processes, it’s hard to know how this will compare to the 32nm and 45nm nodes that appear on more conventional roadmaps. With games like these, it’s easy to see why the International Technology Roadmap for Semiconductors (ITRS) gave up on the idea of naming nodes. Instead, it focuses on actual on-silicon measurements in its estimates of when processes will become available.

Based on what TSMC presented at conferences in recent years, the 40nm process has measurements such as contacted gate pitch - the key one for transistor density - which were consistent with Intel’s more conventional nomenclature. One library supplier pointed out that TSMC’s 40nm process was pretty much its 45nm process but with more restricted design rules.

Until IEDM rolls round at the back end of this year, TSMC is unlikely to publicly disclose the reality of its ‘20nm’ process, although big customers will know what they’re dealing long before that.

What will be a plus point for TSMC, although it sounds a little strange, is that the company will almost certainly be enforcing highly restricted design rules in the 20nm process - but this will be the third iteration of that move. Because of its use of a gate-last manufacturing process at 28nm, similar to the approach used by Intel since 45nm, TSMC already needs to make sure designers use a small selection of shapes in their standard-cell libraries. Gate-last manufacturing tends to provides opportunities for strain engineering but with the downside of being less tolerant to design variation.

As there is no plan to move to extreme ultraviolet and the technique of source-mask optimisation is also on the table - in which the shape of the light beam is tuned to the on-chip structures used on the finest geometry layers - it is going to be straight lines all around as far as chip design is concerned. But much more of the infrastructure for designing that way will be in place by 2011/2012 (as initial production is meant to start at the end of 2012).

TSMC is confident that anyone using gate-first right now will have to switch to doing it the other way real soon now even if their customers have had a bit more freedom in the design department. I guess TSMC sees it as an advantage in saying they have ‘leapfrogged’ the competition in measurements even though it’s the same kind of trick the other camp can do. They have already done the trick of launching a 28nm half node hot on the heels of the originally planned 32nm version of the process. There is plenty of time for Common Platform foundries to turn up and say: “Oh look what we’ve found, a 20nm process.” They might as well call their processes Turbo and Super for all the good this grade inflation does. People doing chip design will have other metrics they are worried about.

What's old is new again

2010-03-25T17:01:25Z

Yesterday, Singapore-based foundry SSMC celebrated its tenth anniversary of silicon manufacture with the news that it was to spend $30m — split roughly 50/50 between R&D and manufacturing — to extend the fab’s lifetime. The investment is meant to keep SSMC’s 200mm production lines relevant in a business now dominated by plants that process larger wafers and which should be more cost-effective.

“We are putting in place a vision that ensures SSMC is in a good position for the next decade or two,” said CEO Jagadish CV.

Jointly owned by NXP Semiconductor and Taiwanese foundry TSMC, SSMC was one the last big 200mm digital logic-oriented fabs to be constructed, opening just ahead of the dot-com crash. It produced the first yielding silicon in October 2000, so barely turned in a quarter’s worth of production wafers before the slump.

After the recovery, 300mm production with 0.13µm copper processes had pretty much taken over from 200mm, which because of the decisions made by production-equipment makers, were stuck on 0.15µm and larger linewidths and aluminium metal interconnect.

Rather than throw in the towel, SSMC changed direction, concentrating on ‘ABCD’ products — analogue, bipolar, CMOS and DMOS. Basically, stuff that wasn’t the standard CMOS turned out by 300mm fabs owned by TSMC and others.

]]> “Many of the products they produce are not linewidth-driven, such as lighting control. All of them require high voltages and high-voltage circuits don’t scale well, so there is no advantage in moving to 40nm,” said René Penning de Vries, senior vice president and CTO of NXP.

But the company did not just stick with the 0.18µm processes that were available when the fab opened in 2000. By pushing the equipment SSMC had, the foundry was able to introduce a 0.14µm process in the first half of the decade. This has gradually expanded from being a 5V-maximum technology to one that can handle voltages up to 100V.

The big shrink
By the end of the year, SSMC expects to have a 0.11µm process running — using pretty much the same equipment the company has used for its other operations — and is looking at introducing ultralow leakage variants, similar to the 180ULL process for 0.18µm linewidths that TSMC launched recently.

“We have even been challenged to do 90nm, not using techniques such as immersion lithography but using the same toolset. Those types of opportunity do exist,” said Jagadish.

The extension to 0.11µm is thanks to the same techniques that have helped make it possible to draw features as small as 40nm using light that has a wavelength four or five times larger.

“For many, many years, people have declared litho to be dead. But it continues,” said Richard Thurston, vice president and general counsel of TSMC, and a director of SSMC. “The same thing has happened here.”

Why do this when there are 300mm fabs out there with similar processes? For a customer like Geoff Lees, general manager of NXP’s microcontroller division, manufacturing on 200mm makes more sense for microcontroller production on a cost-per-die basis.

“The economics of 300mm tend to drive a different strategy,” said Lees, talking late last year about his plans for the microcontroller business.

Production on 200mm lines makes it easier to produce a wider range of peripherals and memory options for 32bit microcontrollers, which, individually, tend to be medium-volume products because they go into industrial and automotive systems. Move to 300mm, and you have to strip out a lot of the variety or eat the die cost of producing large memory arrays and then simply fuse half of it out to produce the ‘cheaper’ low-end versions.

Although there is potential to extend the process roadmap to 90nm at SSMC, the main focus will be on applications such as automotive and lighting, where the demand is for higher voltages. In MCUs, 90nm makes it possible to reduce the size of on-chip memory which can reach into the megabytes on 32bit designs. However, Lees cautions that circuits such as power management units don’t scale well and make it hard to churn out low-end, low-memory devices on 90nm because of the relative size of the power unit and other analogue peripherals.

“It’s hard to get a tiny die at 90nm,” said Lees.

Lights and fast cars
By concentrating on automotive and lighting, Jagadish hopes to extend the operational life of SSMC out as far as 2025. At the moment, 6 per cent of SSMC’s wafers go into automotive. “The board has set a direction for that to go to 20 per cent,” he said.

“The other applications we are looking at are in the low-energy market, such as fluorescent lighting,” said Jagadish. “We are looking at cornering a niche: making silicon for CCFL control with one-chip solutions that we can offer to the lighting manufacturers.”

“This ‘more than Moore’ aspect very much distinguishes SSMC from many of the 8in fabs out there,” said Thurston, who pointed to changes in the chipmaking economy that are putting a new focus on older process technologies.

“Scalability is the key issue. If Moore’s Law had plenty of room to run, then you would go the newer generations more readily. But Moore’s Law is hitting the wall and companies are discovering that scalability doesn’t necessarily matter,” Thurston added. “We are seeing a resurgence in ‘mainstream’ business. We are seeing that, with each of these older generations, starting with 0.18µm, applications in RF or automotive can get a lot more of our technology and IP.

“We have these aging fabs. Let’s make them more profitable and give our engineers more than a 300mm roadmap.”

De Vries added: “The base tecnhology is available. It’s now about building upon this base technology. We see it as very much application driven. Many things are changing and they often require dedicated solutions, with the ability to sense the ambient environment or improve the efficiency of solar cells.”

LED centre
TSMC is not just reworking its older 200mm fabs. The company held the groundbreaking ceremony for a new fab and research centre in Hsinchu that will concentrate on LED lighting and solar cells. The company is spending NT$5.5bn ($170m) to build phase one of the lighting research centre. It’s a move that will see TSMC expand from being a front-end foundry to a supplier of packaged lighting products.

The unit is headed by Rick Tsai, president of new business, who up to last year was CEO of TSMC before chairman Morris Chang stepped in to take up the reins of the company’s core business.

Tsai said at the groundbreaking: “We will enter the market next year by offering LED light sources and light engines.”

The LED fab will be built in two phases. In phase one, equipment will start moving in during the fourth quarter of 2010 with plans to go to full production as early as the first quarter of 2011. TSMC will decide whether to press ahead with phase two based on the results of the first phase.

$170m buys a reasonable amount of production in the older process technologies used for LED production but is a tiny fraction of TSMC’s overall planned capital spend for 2010 of close to $5bn — most of that money will go into 40nm and 28nm capacity expansion on 300mm lines. But lighting by itself could be a huge market as production costs come down and device lifetimes improve.

The key question is whether, for markets such as lighting, because the volumes could be so huge, manufacturers will move to 300mm production over time even for these ‘older’ technologies to get the benefits of scale or trade lower capital spending for higher production cost to get very high long-term return on capital employed (ROCE) scores.

Energy Micro finally takes venture funding

2010-03-18T11:41:06Z

Geir Førre, founder and CEO of low-power microcontroller startup Energy Micro was in no hurry to raise venture funding for his company. Having sold his previous startup Chipcon to Texas Instruments, he was able to use his own money to get Energy Micro off the ground for around. And with some money from the Norwegian government and lead customers, the company had $6m to get to its first product launch, the EFM32 Gecko that appeared last year.

It took $3m, according to Førre, to get the Gecko out of the door and employ, as of October, around 30 people. The remainder was seen as enough to get the company to the middle of this year and has since taken on some more people, taking its headcount to 35. To get further, the company has raised $13m in venture funding. Last year, Førre said Energy Micro was looking for around $10m, arguing that it need not take much to get a fabless startup off the ground and into revenue.

Talking about the initial funding needed for the company, Førre noted: “People say: ‘That’s outrageous. You need far more money to bring up a semiconductor company’. I say: ‘yes, we can do that’.”

Førre said the company spent around $3m to get the EFM32 to market and had “just south of” 30 staff working at its launch. That figure has now risen to 35. The device is built using TSMC’s 0.18µm ultralow-leakage (180ULL) process.

“In reality, even though we are working on very aggressive process technology, mask cost is a small fraction of the money you are burning. The cost is primarily the labour,” Førre said, adding that the company went straight to a full mask, without pursuing the cheaper multiproject wafer option first.

“All of the digital functionality was tested out on FPGA and we used extensive mixed-signal simulation. If you tell people you are designing for a test chip, they will work to that,” said Førre, so he was keen to ensure that the first chip produced at fab should be the real product.

According to Førre, Chipcon spent around $9m before it turned in a profit and was ultimately bought by Texas Instruments.