Shrinking Violence Blog

Forget the gates, it's density that counts for Toshiba

2008-12-21T22:11:00Z

At first glance, the 40nm process presented by Toshiba at IEDM last week looks no great shakes. In a session dominated by 32nm processes, this one seemed not just one generation behind but a bit more than that if you compared its headline figures with the 45nm technologies described by Intel and TSMC in 2007. But a closer inspection reveals a process with a bit more going for it.

When Toshiba says it's a 40nm, the company means the gate measures 40nm. This is a good 30 per cent longer than the minimum gate length quoted by Intel and TSMC last year and puts the transistor more in line with a 65nm or 55nm process – actual gate length has outpaced the notional length contained in each node's title for some years. As a result, figures such as current drive, which control the performance of the core transistors, are lower than those quoted by TSMC. The NMOS transistor of Toshiba's high-speed version of the process has a current drive of 840µA/µm, around 30 per cent worse than the process that turned into TSMC's own shot at a 40nm technology.

But, if you compare with a 65nm process, where transistors often wind up in the 40nm-long range, Toshiba's numbers are par for the course. The bulk technology covered by IBM and the Common Platform partners at IEDM in 2004 shows broadly similar numbers. More importantly, the leakage in the new Toshiba process is lower than in those older processes thanks to the decision to implant nitrogen atoms in the transistor channel, the use of flash-lamp annealing and just a touch of high-k in the gate over the channel, without going all the way to high-k, metal-gate structures.

]]> Among other things, these techniques cut band-to-band tunnelling, one big source of leakage in low-power transistors according to Toshiba. By putting hafnium into an otherwise conventional silicon oxynitride gate dielectric, the gate gets slightly better control over the transistor channel, improving drive current by up to 5 per cent. Toshiba takes this boost to reduce the concentration of dopant atoms in the channel. Why? They are big source of variability in deep submicron devices because you can now count the number of active dopants in a channel in the hundreds. It will not be long before you count them in tens.

The lower dopant concentration cuts the junction leakage and the variability. This gave the Toshiba engineers the confidence to scale the SRAM cell down to just 0.195µm², a little smaller than TSMC's 0.202µm² cell supported on its 40/45nm process. With lower variability, there is less chance of individual cells failing, which helps keep yield high.

The contacted gate pitch for logic is also reasonably competitive with the other 40/45nm processes from the likes of IBM, Intel and TSMC, although a bit looser at 168nm versus TSMC's 162nm.

This is a process that is designed for density and low power consumption not performance and marks the continuing separation between semiconductor processes as feature sizes scale down. Toshiba is not alone in doing this kind of optimisation – favouring gate density over gate length – Panasonic (formerly Matsushita) has been doing the same thing. In consumer electronics, where these processes are aimed, cost is still king. That means optimising for overall die area ahead of optimising for performance. As a result, Panasonic uses longer, more conservative transistor designs.

At the Chipworks meeting after close of play on Tuesday (16 December), senior technical analyst Dick James showed pictures of recent Panasonic processes to underline his point. "Panasonic is an interesting company," said James. "They bring out processes that are leading edge in terms of their [market] timing but they have far less stress and strain engineering than the competition uses. The density all comes from packing the gates closer together."

TSMC pulls the big switch at IEDM

2008-12-18T22:29:43Z

TSMC pulled a switcheroo at the International Electron Device Meeting (IEDM) in a further piece of technology oneupmanship following on from its claim of an early move to 28nm earlier in the autumn.

Director of advanced process development Carlos Diaz was scheduled to talk about the company's 32nm high-k, metal-gate process - one that does not actually appear on TSMC's official roadmap now that 28nm has supposedly taken over. The official proceedings are all about the 32nm process. But when Diaz took to the stage, it was a different story: he was there to describe what the company had done with its 28nm process.

This time, there was to be no confusion similar to what happened with the 45nm process where, by the time TSMC launched it commercially, it had transmuted into a 40nm. This 28nm process has different measurements.

Now, is it really a 28nm process? It depends on how you look at it. I think Kaizad Mistry of Intel was right last year when he said contacted gate pitch is the critical measurement that determines how dense a process can be. And density is the reason why people move to more advanced processes. But, you could also argue that SRAM cell size is just as important, especially now that most chips have big banks of the memory on-chip.

If you look at contacted gate pitch, then what TSMC calls a 28nm process would be a 32nm process at Intel. Diaz reported a pitch of 117nm at IEDM on Wednesday. Intel's late paper on its 32nm process came in with a figure of 112.5nm.

Intel, however, has been more conservative with the SRAM cell the company proposed. However, there is a fair amount of latitude in this metric as there is a clear trade-off between size and noise. The smaller they get, the more noise you see in the SRAM circuits. Too much noise and the circuits begin to fail. TSMC pushed to get a cell that measures 0.13µm². Intel was happy with 0.17µm²

It was a similar story last year in the duel over 45nm, where TSMC showed a smaller SRAM cell but its gate pitch was not as tight as Intel's. This time around, TSMC wants to demonstrate that it has a disinct 28nm process but there is still a question mark over whether this 28nm is not simply a tight 32nm.

All that scratching is pushing the pitch

2008-12-16T03:34:26Z

When I last interviewed Wilf Corrigan, before he moved up to chairman and ultimately parted company with LSI Logic, he argued that the Japanese chipmakers made one crucial mistake in the 1990s. They didn't trust chemical mechanical polishing (CMP).

I have a lot of sympathy for the Japanese technologists. If someone came to you and said: "We know you've taken a lot of care to put down those transistors. They're incredibly delicate structures. That's why we think you should go at the wafer with a Brillo pad and a bucket of acid."

In essence, CMP is a high-tech scouring process. You lower an abrasive pad onto a spinning wafer and you add a chemical slurry and you keep going until you think the wafer has been polished flat. Believe it or not, this works. CMP flattens surfaces other techniques cannot reach. Before CMP, the top surfaces of chips were lumpy affairs. Each layer you put down made it lumpier. It meant there was a limit to how much wiring you could get on the chip. Three layers and you were about done. A section through a chip looked more like a geological diagram of what rock strata look like after a few earthquakes.

The industry could not stick with three layers, they had to go higher. But they had to deal with the lumpiness. The answer was to take the scouring pad to the wafer after putting down another layer of metal. Believing that they could not control the quality of the polishing, the Japanese held back. But the US companies pressed on and started to retake a lead in chipmaking they lost ten years previously.

Intel reckons CMP can do a lot more. And Joseph Steigerwald turned up to IEDM in San Francisco to let them know what. There is an Intel-oriented subtext to his paean to the high-tech Brillo pad: it's a key component of the process used to make the metal gate stacks in the company's 45nm process and, most likely, the 32nm version. Where the rest of the business is focusing on the gate-first approach, Intel reckons that its approach works better. And CMP makes it possible.

The other place where CMP is going to be crucial is going to be in 3D integration, particularly where chips are bonded together and connected using metal vias that extend all the way through the wafer. And this is where another surprisingly reliable technology, reactive ion etch, plays a big role. Etching is arguably one of the most precise tools available to process engineers even though it revolves around pumping noxious gases into a chamber where they can start eating into the silicon. Luckily, those gases don't eat away at the hard masks that seal off portions of the wafer.

For things that look as though they really shouldn't work, CMP and etching have done pretty well for themselves.

Success through hardship

2008-11-22T15:41:42Z

In 2001, James Surowiekci wrote a short piece in the New Yorker on how some of today's biggest companies launched in recessions and made it big. Some of them – GM and Sun Microsystems – aren't looking too hot going into this one but, on balance, the list covers some of the biggest hitters of the US economy.

It contained a important lesson for the semiconductor business:

During a boom, it's easier to raise money and easier to sell products. You'd think that would be a good thing if you were trying to start a business. The problem is that everyone else thinks so, too; when the economy is hot, everyone's an entrepreneur. The more companies there are, the less likely it is that one of them will be able to sustain a lasting competitive advantage, no matter how flush the marketplace is. Starting a business is like investing in stock: you want to buy low and sell high. Launching a company in the middle of a boom is the equivalent of buying JDS Uniphase at a hundred and fifty dollars a share. It could go higher, but the smart bet says it won't.

It's been my argument for some time that the number of companies operating in the semiconductor industry, which includes electronic design automation (EDA), that access to money has been pretty easy, particularly for startups. This allowed situations to develop where you had 20 companies vying for a lead position in WiFi, Bluetooth and other markets.

This helped sucked the potential for returns from the venture-capital industry. Talking to foundry TSMC's customers earlier this year, August Capital partner Andy Rappaport showed graphs that, basically, said too much VC money has been chasing too few good ideas. Most of the money flowed into crowded sectors where the probably of individual success was low.

The problem for the semiconductor industry is that the most crowded sectors tend to be those with the highest volume, with one notable exception: PC processors. There, Intel's near monopoly status and willingness to keep it that way has meant companies attracted to the space rarely survive.

Elsewhere, incumbents have been willing to drop prices to maintain high market share in the hope that the smaller players will drop out. Just ahead of the current recession, we saw that process begin in mobile-phone SoCs. Francis Sideco of iSuppli has argued for a while that, to stay in that game, you need annual revenues of $1bn to stay in the game. And, long-term, if you are not in the top three or four, you don't really have a business.

Companies such as NXP Semiconductors realised this and got out, diverting the R&D money to less sexy but probably more profitable areas such as microcontrollers, a market without many VC-funded startups at all. The only sensible buyer for Freescale Semiconductors' own cellphone-silicon business is a larger player or one with the cash and willingness to do a rollup to get into the big league.

We are now going to see the same situation play out in other markets as the VC drought forecast by Sequoia Capital kicks in and other, more established companies decide to get out of long-term loss-making businesses.

In the short term, we are going to see a lot of people put out of work. However, the semiconductor sector that emerges could be in the strongest position since the early 1990s, a period of slow growth but one where prices firmed so well that chipmakers became investors' favourites. It went sour in the overinvestment-glut cycle of 1995-96 but that is something for tomorrow's chipmakers to watch for.

The startups who are able to make it with little to no additional VC funding for the next two to three years could be in a very strong position indeed, as long as they don't try to face down the cash-rich.

(Via rexblog.com: Rex Hammock's weblog via Samir Husni's Mr Magazine.)

OVP hitches ride on TLM2 wagon

2008-11-21T22:05:29Z

If you don't like stuff about obscure standards in system-level modelling, look away now.

A round-robin email from Simon Davidmann of Imperas and the self-styled Open Virtual Platforms (OVP) group arrived earlier today saying they have added support for version 2.0 of the Transaction Level Modelling standard (TLM), published by the Open SystemC Initiative (OSCI). No, I'm not proud of myself for getting three obscure acronyms into the one sentence.

OVP launched onto the scene just as the work on TLM2 was drawing to a close. The idea behind both is to build fast simulations of hardware designs so that you can debug them. Not only that, you can debug software programs that run on top of that hardware. It's taken since 1994 to get to the point where the electronics industry, or at least the chip-design part, accepts this is a viable way of designing hardware, but it is happening.

Imperas claimed OVP could be much faster than TLM2 and, although it was not meant to be a complete replacement for TLM2, the emphasis within their camp was that you would, for the most part, not need OSCI's stuff. The people behind OVP have, apparently, realised that this was not a viable position and have now decided to add "native TLM2 support to OVP".

If you want to get an OVP processor model that has TLM2 interfaces, you can drop a line to the people at OVPWorld. The OVP claim is that you can get hundreds of MIPS out of their models. As most processor models are written in C and then given a TLM2 interface, I've never been clear why OVP's approach should work out any faster but the system architects out there can try it out.

There is a forum at the OVP website, so I imagine you will be able to ask questions about the OVP-TLM2 interface stuff there.

Déjà vu all over again

2008-11-20T17:57:37Z

The last time I heard the phrase "unprecedented lack of visibility" was in the bloodbath of 2001. The phrase made a prominent return in the Semiconductor Industry Association's 2009 forecast presentation held just ahead of the group's annual dinner in California. George Scalise, president of the SIA introduced the term again to describe what is happening to the chip business right now.

Is it 2001 all over again? The SIA is forecasting for 2009 a decline of 5.6 per cent. In effect, this takes semiconductor sales back three years to 2006. The slump of 2001 had a similar effect, removing the gains of 1999 and 2000 and taking the value of the industry back to around 1998 which was itself a pretty ropey year.

The difference is that the industry's sales shrank more than 30 per cent in 2001 compared to 2000. The fall this time looks far less precipitous. And the situation is different. At the end of 2000, the chipmakers found out their customers had built up enormous stockpiles of inventory and would not need any kit for quite a while. And, with the collapse of the dot.com bubble, their customers were not going to be needing much in the way of electronics either.

This time around, there is no inventory overhang other than the finished goods that consumers have suddenly realised they can't afford to buy. Based on other analysts' figures, the SIA reckon the cellphone and PC markets will shrink by around 5-6 per cent each next year. As these markets account for more than half of chip sales, it's no surprise that the SIA expects to see a drop of around 5 per cent in the semiconductor market.

Life for the chipmakers could actually be worse because pricing has the potential to spiral out of control. Chip prices have been on a downward slope since the end of 1995, punctuated only by tight wafer capacity in years like 2000 or 2004. Although the value of the semiconductor market fell 30 per cent in 2001, the amount of silicon shipped only dropped by 16 per cent. You can see that in the graph below of output and quarterly semiconductor revenues. When demand drops, so does the average selling price of ICs. So, the drop-off could be higher than the SIA's current estimates.

The argument against a big fall in prices is that capacity is much tighter than it was in 2001. The excess of capacity, shown below by process, right now in the most advanced nodes is almost certainly due to the ongoing chaos in the memory business. On the face of it, the situation does not look good right now: the industry is heading for a fall in demand in a situation where capacity was already loosening prior to the third quarter. The figures are from SICAS, the capacity reporting arm of World Semiconductor Trade Statistics, which has figures up to the middle of the year. It takes time to collate the information from so many different fabs, so don't expect Q3 stats for a while.

Because the amount of spare capacity has outstripped what was, up to now, pretty steady growth in unit demand, prices have fallen. Now that unit demand itself is dropping off, the question is what happens to pricing. In previous cycles, shortages and price rises preceded a fall in demand, which led to bigger declines in price.

This time, the chipmakers are reacting much more quickly than they have in the past. They have a much better handle on inventory levels and companies such as Microchip have ordered two- or three-week production holidays to stop their own inventory piling up. Others will probably only take silicon to finished wafers and then store them under nitrogen so they can be packaged relatively quickly if demand turns up for particular product lines. This was a trick used successfully by many of the analogue-silicon suppliers in 2001 to control inventory but still be able to handle sudden surges in demand within a quarter. Without finished wafers, it takes you almost the whole quarter to make anything.

The upshot is that there should not be massive amounts of silicon in the distribution channel to push down prices. The biggest factor, whether richer vendors will make a push for market share using price, is difficult to predict right now. My feeling is that no-one is keen to throw good money away right. There is little point in buying market share when you are not sure your own customers will make it through the next year or two.

In terms of supply and demand, the big producers have already slashed their capital expenditure and they don't plan to spend more in 2009. As demand turns up, production capacity could get tight very quickly. This is a prospect raised by analysts such as Malcolm Penn at Future Horizons and Bill McClean at IC Insights. Originally, they saw 2009 as the year that happens. The recession postpones that event by at least a year.

The result is that falls in price will probably add a few more percent to the SIA predicted decline in market value. But, if enough of the chipmakers keep their heads, the price decline can be kept to a minimum. However, this is difficult to reconcile with the behaviour of the memory companies over the past few years.

On Semi pulls rug from under Microchip

2008-11-18T23:30:37Z

Microchip has been forced to call off its purchase of Atmel. On Semiconductor, which was going to take Atmel's memory, RF and analogue operation off Microchip's hands has pulled out of the deal citing "the unforeseen deterioration in the semiconductor market since we announced our proposal as well as the unprecedented weakness in the financial markets".

On Semi had to borrow to pay the $1bn in cash needed to buy the Atmel businesses it wanted. The rule seems to be right that if you need to get a loan to buy a company in the electronics business right now, you might as well forget about it. It was tough enough in the summer, as Cadence Design Systems found out. In an environment where even IC unit shipments are falling, as SEMI indicated for the third quarter of the year, you need to be really, really sure you want to make that purchase.

Microchip's problem is that 8bit microcontroller sales in general have flatlined in the past few years. The only way to get any movement in sales is to grow market share, which is tough in the 8bit business at the best of times and very tricky in a recession. Microchip benefited from Freescale (then Motorola) fumbling the ball in the late 1990s and ultimately knocked the Texas-based company off the number-one slot in 8bit microcontrollers in 2006. Freescale, however, is larger than Microchip in the wider market for microcontrollers thanks to a longstanding presence in both 16 and 32bit architectures.

One of the few architectures in 8bit to be less than 20 years old, AVR has built up a solid fan base among embedded-systems engineers. The company wanted a core done properly and got Nordic Semiconductor to design one for it that did not suffer the problems of earlier processors. Among other things, the AVR microcontroller drives the capacitive touch sensing technology that Atmel wants to sell to handset makers keen on making their own iPhone-like devices.

Before the semiconductor business ran into a wall in the Autumn, AVR sales grew as much as 25 per cent from 2007 to 2008. Atmel logged just over $100m in AVR sales alone in the third quarter and took in $144m if other products, such as the 32bit ARM-based devices, are included. Microchip's total microcontroller sales for that quarter were just over $217m. Freescale saw its microcontroller sales slip more than 10 per cent to $408m in the third quarter. With Atmel's help, Microchip would be in a position to catch and ultimately overtake Freescale, although Renesas Technology would remain the world's biggest microcontroller maker.

Without Atmel, Microchip has to rely on comparatively new architectures in its portfolio. In the 32bit space, the company has a major challenge: selling a new architecture based on a design by MIPS against not only Renesas but an aggressive line-up of companies with ARM cores, many of whom have agreed on a binary compatibility system that will make it easy for customers to not only switch products but vendors. Microchip came close to buying an ARM licence but, for whatever reason, decided to go it alone with the MIPS option. And the company faces a headwind trying to sell its higher-end 8bit micros against Atmel's.

It was, and remains, a deal that Microchip really wants to do.

Qualcomm joins the top table

2008-11-07T01:59:47Z

Analyst firm IC Insights has put together a ranking for the chipmakers that covers the first three quarters of this year. There are no real surprises at the top: Samsung continues to gain on Intel despite the collapse of the flash memory prices but not many companies have switched places.

It's at the bottom of the top ten where history is being made. For two consecutive quarters and for the first nine months of the year overall, a fabless vendor has sat in the top ten. Qualcomm has surged into ninth place in the rankings, displacing Sony. The company managed it for a quarter last year, according to iSuppli figures. But, this year, Qualcomm's position has become more entrenched. In a business that has traditionally been dominated by integrated device manufacturers (IDM), this is a big change. According to IC Insights, there are now three fabless chipmakers in the top 20: Qualcomm; Broadcom at 19 and nVidia at 20. Pretty soon, we will be counting AMD among their number.

IC Insights has warned Qualcomm may not stay in that position for the full year as the company has forecast a big drop in Q4 sales. But there is a good chance that the mobile-phone chipmaker will be close to the top ten if not actually in it. And, as the fabless business surges on, we can expect TSMC to overtake Toshiba and probably ultimately challenge Texas Instruments for the number-three position - IC Insights is unusual in putting foundries in these rankings - no matter what the wider economy does.

Cadence cuts

2008-11-06T15:15:00Z

Yesterday afternoon, Cadence Design Systems said it plans to cut 12 per cent of its workforce - around 600 positions - and cancel deals with its consultants and contractors. Although the press release and 8K announcing the moves talks of focusing on particular areas, early indications are that the cuts have affected a broad swathe of departments.

The timing of the cutbacks suggests that this, unfortunately, is the first of two or more waves of job losses. As I understand it, this week is the last opportunity for Cadence to make the cuts and see the results fall in its final quarter of 2008. The company said it would complete the restructuring in the second half of 2009. It may be that later rounds will see certain groups being closed or sold off.

"In creating the restructuring plan, we emphasised those market segments where Cadence enjoys a leadership position, such as mixed-signal design, advanced verification and low-power design," Charlie Huang, who is acting as co-CEO for the moment, said in the statement.

The suggestion is that the era of the do-it-all Cadence has passed - the company will now step away from areas where it has failed to build up more than a minority position. The question is how deeply the company will ultimately cut. It's hard to see DFT and DFM remaining. What happens to PCB where the company has a solid if not remarkable share but has lost momentum? IC layout is not mentioned by name but that probably falls into what Huang referred to as low-power design.

Although these moves are clearly bad for a workforce that has seen its leaders stumble from one mess to another, there is a silver lining. If Cadence is not going to do it all, it signals a possible end to the suicidal all-you-can-eat deals its former management forged. If EDA companies go back to competing on the best tool for the job, it's probably the best way they can start to bring back the financial value they lost over the past few years.

I was talking to a Mentor executive yesterday before I heard that the layoffs had been announced and argued that EDA companies will probably stop issuing press releases about mega-deals with customers because the analysts will come to regard them as warning signs rather than good news.

The $8m goodbye

2008-10-30T21:28:20Z

Three of the Cadence Design Systems executives who resigned in the middle of the month have not quite left the building. In a regulatory filing about the resignations, Cadence has revealed that Kevin Bushby, Bill Porter, James Miller and RL Smith McKeithen have each agreed to stay on for six months, earning up to $250,000 apiece, "to provide services to Cadence related to the transition of his prior executive responsibilities".

They will not be the only payments the executives receive on the way out the door from the San Jose-based EDA company. At the end of July, the directors, along with former CEO Mike Fister had their contracts revised. The revisions centred around the benefits, such as healthcare, and payments the men would receive should they be "terminated without cause", which is what happened in mid-October according to the 20 October 8-K filing.

When Fister joined, his termination agreement was structured to provide him with a salary of $24,000 for a year on his departure together with a couple of lump-sum payments: 1.8x salary and 1.8x annual target bonus. In July, shortly after the cancellation of the bid for Mentor Graphics, Fister's contract was altered to provide him with a total of four times his peak annual salary. He earned a salary of $1m in 2007.

The termination contracts for Bushby, Porter and Miller, as well as acting co-CEO Kevin Palatnik, were also tinkered with. Unlike Fister's, the changes were not as substantial but confirmed that Bushby, Porter and Miller would receive roughly double their respective annual salaries. In Bushby's case, that means a total of $1m. Porter would net $900,000 and Miller $800,000. McKeithen's contract was altered at the start of April to pay him up to $800,000 on departure.

Two years' worth of the former directors' options also vest on their leaving. However, given how far underwater they must be right now, partly thanks to the misplaced $24m announced last week, that is not likely to mean much.

Totalling that lot up, it will cost Cadence in the region of $8m cash to say goodbye to the bulk of its former senior executive team.

And the costs keep rising for Cadence with two legal firms deciding to file class-action suits against the company over the events that led to its sudden loss in share value. Dyer & Berens and Federman & Sherwood have filed separate actions just today. Another three legal firms are understood to be looking at class actions.

Oops, we put $24m in the wrong place

2008-10-22T21:08:26Z

If you were wondering how things are at Cadence Design Systems, which saw its CEO and other execs resign last week, you are going to have to wait a bit longer. Less than half an hour before the Q3 conference call was meant to start, the company claimed it had discovered a problem with its Q1 figures and was going to have to go back and restate them. As a consequence, Cadence decided to postpone the Q3 results and the accompanying conference call.

"Cadence initiated the review after preliminarily determining during its regular review of its third quarter results that approximately $24 million of revenue relating to these contracts was recognized during the first quarter of 2008, but should have been recognized ratably over the duration of the contracts commencing in the second quarter of 2008. Cadence expects to restate its financial statements for the first quarter of 2008 and the first half of 2008 to correct the revenue recognition with respect to these contracts.
"Cadence will release its third quarter 2008 financial results and conduct a Webcast as soon as practicable."

I wouldn't expect a lot of warning when that conference call actually happens.

Dear Sandisk, when you come round please make sure it's on all fours

2008-10-22T15:02:24Z

Samsung has decided to walk away from its planned takeover of Sandisk, but made sure it left visible wounds on the hapless flash-card maker. And, perhaps worst of all for Sandisk's current management, signalled to the markets that a deal is still possible but at a much-reduced price. The decision gives Samsung a lot more options over what it can do with all the cash it has in the bank in an environment where companies with heavy borrowings have suddenly become vulnerable.

The first paragraph is standard fare in these letters. Samsung CEO Yoon Woo Lee expresses disappointment with Sandisk's unwillingness to negotiate a deal. The gloves come off in the second paragraph - and reveal a pair of bejewelled knuckledusters:

"Nevertheless, we have obligations to our own shareholders which require that we take a disciplined approach, particularly with respect to significant initiatives such as this. That disciplined approach requires that we squarely face the growing uncertainties in your business, which may continue to deteriorate in this difficult economic environment and further impact your standalone value. Your recently announced third quarter results serve only to illustrate this risk. Your surprise announcements of a quarter billion dollar operating loss, a hurried renegotiation of your relationship with Toshiba and major job losses across your organization all point to a considerable increase in your risk profile and a material deterioration in value, both on a stand-alone basis as well as to Samsung."

And then Lee rounds it off with:

"As a result of these developments, we are no longer interested in acquiring SanDisk at $26/share."

To sign off, Lee wishes Sandisk's management well in a kind of "now that you're lying in the street try not to get run over" way.

Cadence waves goodbye to Mike Fister, but he's not alone

2008-10-15T18:51:49Z

There's a serious case of irony failure on the Barron's blog that is one of the first stories to appear online (aside from the press release itself) marking the resignation of Cadence Design Systems CEO Mike Fister. "What a surprise," remarked 'John'. The next commenter didn't quite get the joke but laid in with the perceived reasons why Fister got the cho...er, walked.

I didn't see the news until I got out of the radio silence of the underground bit of the BERR Conference Centre in Victoria Street this afternoon and, frankly, I wasn't going to cough up for WiFi in what is meant to be a government building for business. (There are, apparently, two picocells there. If anyone finds them, please let me know.)

It was both a surprise and inevitable. It was clear that Fister was no longer Mr Popular at Cadence, assuming there had been a period when he was. At an analysts event in September, CFO and now co-CEO Kevin Palatnik used faint praise to damning effect on one of Fister's strategies. This was just after telling analysts about the news that hasn't happened yet but will next week during the Q3 earnings call - that Cadence has potentially a lot of layoffs to make. This is from my online story of a couple of weeks ago at the IET's website:

At a September conference organised by Deutsche Bank Securities, Cadence chief financial officer Kevin Palatnik indicated that the company would make layoffs this year in a bid to improve operating margins. “I believe we can get back to 25 per cent [operating] margins. In the near term, we are very focused on expense management. So, we are looking at resizing the company. Our goal is, in the Q3 earnings call, to be public about our expense management actions. We will resize the company to the lower [sales] base plus the lower growth that we see in the next three to four years.”
Palatnik said attempts to improve pricing for EDA tools, in a market where tool complexity is increasing but the user base is not, did not pay off: “[CEO] Mike Fister came into the company in 2004 and one of his early initiatives was to stratify pricing by product capability, so we had good, better and best pricing...We stratified that [pricing] based on feature and function. Frankly, it has been moderately successful at best...We see some benefits [from stratification] at the high end in some sub-segments of our business but, overall, business has been relatively flat.”

When I heard the last bit on the recording, I thought that Fister was a goner. It's odd for a CFO to align his boss with a failed strategy unless that boss is not long for the company. However, rumours suggested that Fister was to be given "another chance" by the board to turn the company around after the failed attempt to buy Mentor Graphics. If Fister was to get another chance, the board clearly changed its mind.

Although we may look back at this in the context of extensive layoffs next week, What was surprising about today's news was the departure of some Cadence stalwarts. Field operations vice president Kevin Bushby and former head of Cadence in Europe is going as is Bill Porter, who had moved out of the CFO chair. Porter and two other veeps are not being replaced.

The guidance that Cadence has given for its Q3 results is the same as the range provided by Palatnik in the Q2 call, including a 26 cents per share or so loss, so no real surprises there. The one to watch out for next week is the full year amount, which was, in the middle of Q3, around $1.13bn in sales with earnings per share around 52 cents.

The Common touch

2008-10-08T12:51:27Z

AMD has bought itself some time with the decision to hive off its manufacturing operation and has silently answered the question of what it is going to do about getting its own products made. It is just about conceivable that AMD's core processor business might follow ATI to Taiwan, where the graphics chipmaker has had its products fabbed for years.

If AMD really wanted to frighten the horses, it would do exactly that. If anything, AMD could well be set to pull business away from the Taiwanese foundries such as TSMC. But, in setting up The Foundry Company with money from Abu Dhabi - an operation that almost certainly has to join IBM's Common Platform group to gain any business at all — AMD is more or less set on a course to even tighter links with IBM. AMD's silicon-on-insulator (SOI) process uses technology licensed from IBM, although the x86 processor maker has not joined Common Platform to date.

TSMC has clearly been angling for processor business in general, having decided to introduce a high-k, metal-gate process at what it calls the 28nm process node. Processors, graphics processors and field-programmable gate arrays (FPGAs) are the target for this version of the process. AMD's endorsement would have been a major boost even for the world's runaway number-one foundry. However, TSMC has never been keen on SOI whereas a number of vendors in the Common Platform camp have worked with it. IBM is the obvious candidate for external SOI production. But Samsung has worked with SOI in the past and, although a tiny player in the foundry business, is the fastest-growing. And it has a full 300mm fab dedicated to the foundry business, something that the The Foundry Company won't.

Bill McClean of IC Insights put out a note last night on AMD's stated funding plans for the fabs that will go into The Foundry Company, assuming that the deal - with its non-US source of funds - clears the regulatory hurdles and a possible spat with Intel over patent rights. It concluded:

"Given that Foundry Company’s capital spending budget for the next five years is forecast to be less than AMD’s capital spending outlays over the previous five years, it is highly unlikely Foundry Company will help AMD gain additional marketshare. In fact, AMD will be lucky to sustain flat marketshare in the MPU segment. Moreover, a significant portion of the Foundry Company’s budget must be allocated to the new foundry business, and this, of course, will take away precious spending needed for MPU production!"

The capital expenditure for the company next four years will be between $3.6bn and $6bn. That sounds like a big heap of money but even at its maximum it's only about half of what TSMC spent in the last four. Not only does this money has to be divided between AMD and foundry-oriented gear, which will probably mean additional equipment for bulk silicon wafers on top of those used for SOI, it's guaranteed to be less than what AMD itself spent in the past four years.

McClean also noted: "There is a lot more to being in the IC foundry business than hanging out a sign and announcing you are a foundry, just ask some of the Malaysian and Chinese foundry startups about the difficulties of gaining marketshare in this segment of the IC industry."

In the past five years, TSMC got the recipe right and built up a formidable reputation for getting it right. You often hear fabless companies say, when asked who they're using: "TMSC, of course." Now, you have to add a little dose of scepticism. Like Fight Club, TSMC's customers are wary of talking too much about their relationship with the foundry except in those rare situations where TSMC tows them around to tout the company's advantages. However, you don't hear the same things about many of the other foundries and trust in a foundry's ability to deliver is probably the biggest contributor to their continued growth.

It's not all TSMC. SMIC picked up some loyal customers early on, partly due to the seemingly tireless Richard Chang who, like TSMC chairman Morris Chang, spent many years at Texas Instruments. SMIC has overtaken Common Platform member Chartered Semiconductor Manufacturing but it's been hard work and the company remains a fifth of the size of TSMC.

There is some good news for The Foundry Company in terms of its position. AMD's annual sales are close to $6bn. If you split that in half to come up with what The Foundry Company's sales might be to AMD, then that puts the business fairly close to number-two foundry UMC. Equally, the dominance of one company in the foundry's business is unlikely to attract other fabless players unless the company can bring something the other foundries, or Common Platform suppliers cannot.

For TSMC, the situation will be interesting. Suddenly, with The Foundry Company onboard, the Common Platform group would as an aggregate be able to claim number-two status. Total sales would still lag TSMC but, in perception terms, the group could claim to provide a serious alternative to TSMC and provide the thing that the big fabless companies keep saying they want - true multiple sources for the same products. And that makes the strongly capitalised Samsung even more of a threat to TSMC.

Samsung looks to build high in SanDisk bid

2008-09-17T14:00:08Z

Charles Arthur blogging at the Guardian has pointed to the loss of confidence in the technology sector as helping to bring on a bid from chipmaking giant Samsung for flash-memory company SanDisk. Amid a massive glut of NAND flash, SanDisk has taken a pummelling in the stock markets this year. On the one hand, the company looks cheap. But not many people want to take a risk on a rollercoaster business like NAND flash, especially not now when borrowing is relatively expensive.

That is, unless you're Samsung. The company already has a massive chunk of the NAND flash business. Does it really want more when it's been busily shutting down older fabs to take some capacity out of the market and shift production to newer, more cost-effective fabs?

For SanDisk, yes. The company might look troubled but it has some important technology buried inside its research labs. There are big changes coming in the flash business and Samsung is prepared to spend a lot of money to make sure it is ready. The problem is that conventional flash technologies are running out of steam. You can make the memories smaller, but it's getting harder to get them to store any data reliably and the cost reductions aren't coming through, which is a big problem for a commodity market like this.

One answer is to build high. NAND memories are arranged as strings of bits, all laid out neatly in rows. Stack the strings vertically and suddenly you have increased memory density 16-fold. If you do this, you don't have to make the memory cells smaller to get much denser storage. You can even make them a bit bigger and buy some time for the coming generations. This is what SanDisk demonstrated with Toshiba last year.

Samsung is very keen on 3D flash memories as well, but is building them up layer by layer, which looks to be a more expensive process. Assuming they can translate it into production, the SanDisk/Toshiba memory is much simpler and cheaper. The two companies have also collaborated on 3bit and 4bit-per cell memories. These are slower than today's flash memories but potentially a lot cheaper. And, in media players, speed does not matter all that much.

In the long term, the smaller players will simply get shaken out of the NAND business, leaving more to the likes of Samsung and number-two manufacturer Toshiba when the business finally turns up. By buying SanDisk, Samsung gets more flash capacity. It stops having to pay $0.5bn a year in royalties. It gets an armlock on 3D and multibit technologies and it gets to disrupt Toshiba's plans. It's not going to be fun competing with a much larger player who has a share in the same technology you planned to use.

Plus, cash-rich Samsung can force Toshiba into making a counter-bid, tying up its nearest competitor in a proxy war that it cannot really afford to win financially. But, unless Toshiba is betting on US regulators coming to its rescue - I would expect Micron Technologies to make a complaint at the very least - Toshiba has little choice but to make a bid of its own.