Cadence tries to avoid the Tality trap

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When Cadence Design Systems said last week it was getting back into the business of supplying intellectual property (IP), my first reaction was: “Oh look, they’ve reinvented Tality.” I wasn’t alone. Just about everyone who I talked to afterwards before and during the International Electronics Forum in Dresden said more or less the same thing: “It’s Tality all over again.”

Back in the late 1990s, as startups rushed to get chips into the market and cash out with an initial public offering (IPO), the Tality subsidiary seemed to Cadence a good way to get more money out of the design business. Tality was to be a ‘design factory’ for chips. You came in with an idea, Tality - for a fee - provided you with the chip design that you could then get fabbed at a foundry.

There was only one problem: Tality lost money on the deal. It could never charge enough to cover its costs and, eventually, the whole operation was wound up or sold off in bits.

One part of the Tality plan was to develop commonly used blocks of IP and use it across different projects, with the advantage that the engineers knew how to tie it together. Fast-forward ten years and you have a broadly new management team in at Cadence trying to work out how it expand its business without having to commit to the expensive R&D needed for deep sub-micron chip-design tools.

Having realised that making lumps of IP work together is not often straightforward, the team came up with the idea of doing a lot of that integration work for the customer. Other than the name, it sounds as though a part of Tality rides again.

vishalkapoor-1.jpgVishal Kapoor, vice president of product management at Cadence and responsible for the new IP operation, said at the launch in Germany: “We don’t want to be Tality and do all the design services for you. We want to provide integration-ready components. The services we provide are in support rather than a replacement for design.”

To prevent the service element from spiralling out of control, the customer’s ability to edit the IP will be restricted. “The methodology is constraining: we have optimised it for you. Thou shalt not touch. But, to take that ability to modify away from customers, you have to give them something else. So we assure them compliance,” said Kapoor.

Cadence will start with common protocols such as USB and provide everything from the controller to the physical-layer transceiver. To avoid having to build a complete IP-design team in the way that Synopsys has - and which has built up a bundle of protocol-IP already in the past ten years - Cadence is licensing IP cores themselves from other players, such as IBM, RapidBridge, GDA and Sonics. What the Cadence team then does is bolt the pieces together, make sure they play nicely together and provide that as one chunk of logic and software.

Ultimately, if the first phase goes according to plan, Cadence will assemble these stacks into combos on the basis that where you find USB, you also find networking interfaces and memory controllers.

If you’re thinking this concept of providing pre-integrated IP is familiar, the overall concept is not far from what ARM tried to do with Primexsys in the first half of the past decade. Bits of this still exist but the UK processor designer gave up on trying to develop entire platform definitions under the Primexsys brand after the company discovered it was trying to push water uphill with its offering.

The desire to customise IP to suit a particular SoC’s bus structure is Cadence’s biggest headache. But, with millions more transistors now available to chipmakers compared with five or ten years ago, the desire to mess around with a titchy little USB controller has to be waning, even if it’s taking years for engineering teams to look at IP more as a black box.

Kapoor is under no illusions as to how chipmakers want to buy IP. “The market is moving away from IP-based royalties,” he said.

By sub-licensing IP, Cadence is constrained by the terms of its suppliers but the understanding that chipmakers, although they may tolerate royalty payments for ARM processors and specialised cores, they are not going to pay a few cents for each protocol controller they put on-chip. An upfront licence fee is quite enough, thank you. This arrangement is somewhat more difficult for a company such as ARM to swallow than it is to Cadence, which is used to licences, subscriptions and maintenance deals.

A further constraint on Cadence is on who fixes the bugs in the cores themselves. Those fixes need to be done by the supplier rather than Cadence. In principle, this should not be a problem but, with many of the bugs that now turn up in integration tests, determining fault is not always easy and could lengthen the process of getting working IP combos out of the door.

When talking about its IP plan, and implicitly pointing to Synopsys as the other major player, Cadence likes to call its approach to IP provision “open”. This openness is largely based on the fact that Cadence is not writing its own RTL rather than any grand plan to go open source.

However, Cadence aims to provide a way for IP suppliers not on the initial list to get onboard by qualifying their own cores through the same process used by the company’s integration team. This will help Cadence scale up the operation, Kapoor said.

“Once the qualification criteria are established, we will offer those criteria to third parties to qualify against and sell,” Kapoor added.

If the company pulls this one off, it might provide a de facto alternative to what the IP industry currently has for estimating the quality of an individual IP core. Right now, that’s a self-certification spreadsheet that evokes little more than wry laughter around the industry whenever someone mentions the possibility of a revived IP quality standard. A published qualification process could help the wider industry.

Update: Cadence is going to do a bit more of its own design with the $315m acquisition of memory IP specialist Denali, and in real money too, not shares.