IP's a slow burner

| | Comments (2)

Cadence Design Systems has decided that semiconductor intellectual property (IP) is important to the chip design and so has bet fairly big on its $300m cash acquisition of Denali together with a plan to pre-integrate IP from other suppliers.

Let’s have a look at the rationale. Design costs keep going up - in proportion to the number of gates you can squeeze onto an integrated circuit (IC).

“The only thing that scales is IP. You can’t move to the stratosphere in terms of abstraction. You have to use IP…The SoC battle is won or lost over the quality of IP…IP reuse will go up to and beyond 90 per cent of the die. But having multiple IP vendors for one chip design brings challenges, so you will qualify IP vendors rather than individual IP cores. Everything points to consolidation.”

Oh no, wait. That wasn’t Cadence. Those were the words of Raul Camposano in mid-2004, who was then Synopsys CTO. Sounds a lot like the Cadence rationale doesn’t it? But it doesn’t say a lot for Cadence’s new found strategy rewriting the rules of EDA. It’s easy to see how an EDA-plus-IP strategy can develop because you only have to look at what has happened at Synopsys, the only major EDA vendor so far to have made a living at IP. Mentor Graphics had a go but that did not turn out so well and the company got out of the business.

Since the Internet bubble, the share of Synopsys’s revenues from IP has hovered around 6 to 8 per cent according to a succession of 10K annual-report filings. The share was as high as 10 per cent in 2001 but this was before the company acquired Avant, when the IP share slid to 5 per cent.

Synopsys’s 2003 revenues totalled $1.2bn. In 2009, they came to $1.4bn. IP revenues averaged about 7 per cent of the total in 2003, providing Synopsys with $84m just before Camposano made his prediction about the rise of IP. Now, they amount to $140m. That’s about 9 per cent per year, about the same as the semiconductor industry’s long-term average growth. It’s not transformative growth by any means. This wasn’t because Camposano was wrong - far from it - just that the increased use of IP does not necessarily translate into massive sales.

As chip capacity increases - which pulls in more third-party IP - design starts go down, slowing down the growth of the IP suppliers. You could argue that maybe Cadence has entered the market at just the right time. But it takes time to establish a reputation as a stable, reliable IP supplier as Synopsys chairman and CEO Aart de Geus pointed out in the company’s most recent results conference call. Buying Denali gives Cadence greater credibility in the market than simply bootstrapping its own operation but it will take time for the company to see a return on its $300m, if it sticks at it.


The comparison to Synopsys's earlier move into IP is inevitable. But do you think it makes a difference that we are talking more about Verification IP in regards to Denali? Will the value of the purchase get diluted by bundling with the tools, r will it create leverage for more tool sales?

Respondent to my survey (http://bit.ly/bEFDjQ) are leaning toward the negative in answering the question "Do you think that Cadence's purchase of Denali will provide a benefit for designers?"

It's a bit of both with Denali. The purchase provides Cadence with a decent stock of memory controller cores that fit in nicely with the idea of the company building Primexys*-style subsystems. However, the company could have obtained them from Denali in the way it's sub-licensing cores from other IP suppliers. No purchase necessary.

The verification IP portion of Denali provides Cadence with a reason to buy the company, although it is hard to see that bringing in the cash quickly. You have a large group which has generated a number of VIPs for blocks that are central to Cadence's claimed strategy. As a part of Cadence, that group now has a reason to tie those VIPs together to do super-VIPs, as it were, to test complete subsystems.

It might help drive tool sales if those super-VIPs only work with the Verisity environment - while keeping support for Synopsys etc within the component VIPs. However, Cadence's IP subsystems will still only be a portion of the total IP bought by most SoC makers, so whatever they do will have to fit in with what those customers are using in terms of verification. Tying the super-VIPs to the tools would hurt IP sales for those SoC makers who don't want to use e etc. (However, that might not matter if Cadence execs come to the conclusion that lots of seats of Verisity coverage and e easily outweigh IP licence sales - Cadence isn't planning on using a royalty model for IP).

* Of course, no-one has yet demonstrated that this approach is a commercial winner. However, it does make conceptual sense to have someone come up with decent, power-efficient ways of getting USB etc to talk to memory and sell it as a package.