May 2010 Archives

Cadence Design Systems has decided that semiconductor intellectual property (IP) is important to the chip design and so has bet fairly big on its $300m cash acquisition of Denali together with a plan to pre-integrate IP from other suppliers.

Let’s have a look at the rationale. Design costs keep going up - in proportion to the number of gates you can squeeze onto an integrated circuit (IC).

“The only thing that scales is IP. You can’t move to the stratosphere in terms of abstraction. You have to use IP…The SoC battle is won or lost over the quality of IP…IP reuse will go up to and beyond 90 per cent of the die. But having multiple IP vendors for one chip design brings challenges, so you will qualify IP vendors rather than individual IP cores. Everything points to consolidation.”

Oh no, wait. That wasn’t Cadence. Those were the words of Raul Camposano in mid-2004, who was then Synopsys CTO. Sounds a lot like the Cadence rationale doesn’t it? But it doesn’t say a lot for Cadence’s new found strategy rewriting the rules of EDA. It’s easy to see how an EDA-plus-IP strategy can develop because you only have to look at what has happened at Synopsys, the only major EDA vendor so far to have made a living at IP. Mentor Graphics had a go but that did not turn out so well and the company got out of the business.

Since the Internet bubble, the share of Synopsys’s revenues from IP has hovered around 6 to 8 per cent according to a succession of 10K annual-report filings. The share was as high as 10 per cent in 2001 but this was before the company acquired Avant, when the IP share slid to 5 per cent.

Synopsys’s 2003 revenues totalled $1.2bn. In 2009, they came to $1.4bn. IP revenues averaged about 7 per cent of the total in 2003, providing Synopsys with $84m just before Camposano made his prediction about the rise of IP. Now, they amount to $140m. That’s about 9 per cent per year, about the same as the semiconductor industry’s long-term average growth. It’s not transformative growth by any means. This wasn’t because Camposano was wrong - far from it - just that the increased use of IP does not necessarily translate into massive sales.

As chip capacity increases - which pulls in more third-party IP - design starts go down, slowing down the growth of the IP suppliers. You could argue that maybe Cadence has entered the market at just the right time. But it takes time to establish a reputation as a stable, reliable IP supplier as Synopsys chairman and CEO Aart de Geus pointed out in the company’s most recent results conference call. Buying Denali gives Cadence greater credibility in the market than simply bootstrapping its own operation but it will take time for the company to see a return on its $300m, if it sticks at it.

Infineon Technologies has decided to drop its complaint against memory maker Elpida in what looks to be a case of patent stalemate.

The German company decided to go to the US International Trade Commission in February, claiming that Elpida had infringed some of its patents. As Infineon backed out of the memory business with the closure of Qimonda, it looked as though the German chipmaker aimed to claw back some cash by finding infringers of memory-related patents. It has wound up with a patent cross-licence which, although is not to be sniffed at, doesn’t sound like a wholesale victory.

To get the money rather than the cross-licence from patenting it’s important not to be actually making stuff (and so it’s just as well that most semiconductor patents are in the hands of companies making stuff otherwise the whole industry would grind to a halt).

When Cadence Design Systems said last week it was getting back into the business of supplying intellectual property (IP), my first reaction was: “Oh look, they’ve reinvented Tality.” I wasn’t alone. Just about everyone who I talked to afterwards before and during the International Electronics Forum in Dresden said more or less the same thing: “It’s Tality all over again.”

Back in the late 1990s, as startups rushed to get chips into the market and cash out with an initial public offering (IPO), the Tality subsidiary seemed to Cadence a good way to get more money out of the design business. Tality was to be a ‘design factory’ for chips. You came in with an idea, Tality - for a fee - provided you with the chip design that you could then get fabbed at a foundry.

There was only one problem: Tality lost money on the deal. It could never charge enough to cover its costs and, eventually, the whole operation was wound up or sold off in bits.

One part of the Tality plan was to develop commonly used blocks of IP and use it across different projects, with the advantage that the engineers knew how to tie it together. Fast-forward ten years and you have a broadly new management team in at Cadence trying to work out how it expand its business without having to commit to the expensive R&D needed for deep sub-micron chip-design tools.

Having realised that making lumps of IP work together is not often straightforward, the team came up with the idea of doing a lot of that integration work for the customer. Other than the name, it sounds as though a part of Tality rides again.