Transistors stand up for denser DRAM


When Swiss startup Innovative Silicon first got going, the company argued that its memory technology could be the thing that drives people towards silicon-on-insulator (SOI) wafers. Despite a strong push by companies such as AMD and IBM, SOI remains a minority choice. All the rest of the action is on bulk silicon wafers.

Following a shift from trying to license its one-transistor memory technology for use alongside logic transistors on system-on-chip (SoC) devices - AMD was the first major licensee — ISi decided a year or two ago that it had a better chance of getting DRAM makers to adopt it before trying to tackle the embedded-memory market again some time in the future.

The DRAM makers have had to come up with increasingly exotic ways to squeeze the bit-storage capacitor into tighter and tighter spaces. ISi is betting that one day real soon now, space is going to win that battle.

By storing a much smaller charge in the body of a transistor, ISi’s Z-RAM could potentially save space — you only have to have a 1T cell, not a 1T-1C cell as with conventional DRAM. But DRAM makers are not in a hurry to move to SOI — they like their wafers to be cheap.

So, ISi has moved in the other direction: away from SOI and into bulk silicon.

“I continue to bump into people who think we’re an SOI company,” said Mark-Eric Jones, president and CEO of ISi. “We are not doing any work on SOI. Everything we do now is on bulk silicon.”

The main change is a new transistor design that takes a planar transistor and rotates it 90° so that it passes current vertically. Although it looks at first like a finFET design from the schematic, and the company has done plenty of work on finFETs, this is a different structure that allows a gate to be placed on either side of the transistor body roughly where the sidewalls are found in a conventional device. sandwiched between the contacts and the transistor body itself.

“What happens is that the minute you turn the transistor so that it is vertical, you can maintain a reasonable gate length without impacting the density of the memory,” said Jones. “You don’t have to shrink the stored charge so much as you scale the lithography. Effectively this is the advantage of a 3D structure. We can scale for decades before this runs out of steam.

“By shifting to the 3D vertical device, there is now no need for SOI and you can use just bulk silicon,” Jones added, which makes the structure compatible with the processes used in practically all DRAM fabs.

Typically, the vertical transistors are made before the logic and sense-amplifier transistors that complete a memory array.

“Basically we get this working with a DRAM process with very little change,” said Jones. For the test chip, developed with licensee Hynix Semiconductor, he added: “We didn’t even change the mask set for the planar ones much. You have to arrange a junction at the bottom and at the top, but this is all done before you build your normal transistors. It was surprisingly successful in that the first lot was functional, which does not happen often in this type of work.”

A second change is a reduction in operating voltage to 1V and, potentially, below. Jones said the voltage reduction has benefits beyond compatibility with DDR3 and later versions of the DRAM standard. “It also improves long-term reliability. With 1V we are now out in the region of 1015/1016 operations with no degradation.

Sungjoo Hong, vice president of DRAM at Hynix, said in a statement: “The advances in power and voltage demonstrated in our 54nm test chips show that the Z-RAM technology has solved the most challenging issues we have seen with floating-body memories. These results validate that the Z-RAM technology has great potential replace DRAM over the next few memory generations.”

Hynix and ISi have submitted a paper on the new design to the 2010 VLSI Technology Symposium, which takes place in June.

It’s tough for any new memory technology to make it into production. Energy Conversion Devices has been banging away at chalcogenide-based phase-change memories for 40 years and those memories have only just made it out of the lab in the past couple. But, if the ISi memory proves reliable and manufacturable, it could cut costs by about 30 per cent — partly through easier manufacturing and partly through higher effective density — compared to 1T-1C designs in the 30nm-40nm range of process nodes that memory companies are now moving towards.