At the TSMC 2010 Executive Forum, Yoji Hino from Fujitsu talked about the company's move to a fab-lite operation with the shift to 28nm. Although the Japanese company has its own fabs able to turn out 40nm devices, it will use TSMC for 28nm production.
One issue that Hino covered was the impact that the I/O ring has on device scaling from 40nm to 28nm. Unless you stuff the device full of transistors the I/O ring on wirebond devices can quickly dominate the cost because the pads don't scale anywhere near as fast as SRAM cells and logic gates. Analogue also generally doesn't benefit that much from scaling, except in terms of switching speed.
Hino presented a chart that showed good scaling from 65nm to 40nm for a device with 20 million gates of logic and 15Mbit of SRAM plus some analogue. On a 65nm process, this measures 10.1mm on a side. On a 40nm process, the dimensions reduce to 7.3mm on a side, a reduction of 48 per cent. However, the increasing dominance of the I/O ring and the analogue means that the 28nm device sees a slightly smaller reduction in area: 41 per cent for a chip that is 5.6mm on a side.
To stop the I/O ring from being too much of a burden, Fujitsu and Toshiba are cutting the pad pitch from 25µm to 22.5µm for staggered pins. The single-row pitch will drop from 40µm to 35µm. As smaller devices on 40nm could benefit from a reduction in I/O pitch, the older process will, apparently, also have the smaller staggered-pin dimensions from the end of the year, when 28nm is supposed to go live. The single-row pitch on 40nm will remain unchanged, presumably on the assumption that if a device is only using a single row of pins around the edge, it's hardly going to be pad-limited.