The next generation of FPGAs from Altera won't be quite as programmable as the last - although you will be able to flip some of the logic inside them as they run. For the generation of FPGAs to be made on a 28nm process, Altera is making several changes.
One change is the merging of HardCopy - the mask-programmed gate array used to provide fixed versions of customer design for less money per die - with the mainstream programmable logic family of Stratix parts. Another is the decision to finally adopt partial reconfiguration so that parts of the logic can be switched in and out while the rest of the system is still running.
"Partial reconfiguration has been around for a long time," said David Greenfield, senior director of Altera's HardCopy business unit. "But this is a fairly significant shift for Altera."
Altera's argument is that it can make partial reconfiguration more tractable for designers through the incremental compilation supported by its Quartus design tool. Essentially, blocks that are to be switched in and out are compiled and then fixed as sub-chips so that when changes are made, any rerouting is carried out inside the chunk of FPGA set aside for them.
The commercial argument for partial reconfiguration, and a number of other changes in the upcoming 28nm family, revolves around the communications business. The idea is not to have the reconfiguration happen many times while the system is running but make it easier to ship one piece of hardware and then configure it for the specific interfaces that the system has to deal with in situ.
The company is staking the future of Stratix on a resurgent communications business. "What is driving the most increased need for processing is video. YouTube last year had more traffic than the entire internet in 2000.
"Our customers are now looking for 400Gb/s systems and a move from 3G wireless to 4G and LTE," Greenfield claimed.
To get an FPGA to cope with 400Gb/s, you need a lot of parallel processing which, according to Greenfield, will drive migration to denser 28nm devices. "You need something in the 320K logic-element range to do 100Gb/s."
A back of the envelope calculation implies a fourfold increase in density needed to get to 400Gb/s with no increase in clock speed. "We can't do it at 40nm. The biggest reticle-busting die we have at 40nm is 530K logic elements."
Even 28nm falls a bit short, not just on density but on power. "We used to get a 20 per cent reduction in core voltage with each generation," said Greenfield. "It will probably drop from 0.9 to 0.8V at 28nm. That reduction isn't going to buy us a lot in terms of active power. Plus you have higher leakage power to contend with."
So, by moving to 400Gb/s transmission, wireline communications vendors would get almost no power reduction, which is not good news when institutions such as Bell Labs are clamouring for energy savings in internet infrastructure equipment.
One answer is to bake into hard logic as much as you can. That is where HardCopy comes in. “Embedded HardCopy blocks will be a new way to improve density,” said Greenfield.
Although less dense than standard-cell ASIC circuits - by about a factor of two according to Greenfield - the HardCopy gate-array sections are way denser than FPGA and, because they use a fraction of the transistors, use less power. Even for its own hard cores, Altera is beginning to favour HardCopy because it's cheaper to design with.
“We have used hard blocks in our architecture for more than ten years, implementing them using standard-cell technology. What we are doing in this generation is using HardCopy functions to get there. It lets us deliver different flavours of the products to customers that fit the needs of their applications.
“If there is a way for us to drop the cost of doing product variants, then it allows us to do more and provide more market-specific products,” Greenfield added.
FPGAs made using the 28nm will have strips of logic array designed for HardCopy alongside a larger fabric of fully programmable logic. Initially, Altera will use the HardCopy area to do its own market-specific products. “But it is envisioned that it will be available for customers to use as well,” said Greenfield.
Because of the tenfold difference in density, you won't need a lot of die area set aside for HardCopy to implement a full FPGA's worth of circuitry. And keeping down the area needed for reconfigurability is where the partial reconfiguration comes in.
In terms of schedule, Altera is not saying when the first parts will be available. However, 2011 seems a reasonably safe bet as TSMC is meant to have the process running by the first half of that year. The FPGA maker has already done a lot of prototyping, using the same approach as it did for 40nm - an approach that Greenfield claimed helped the company deal better with yield issues at TSMC than some of the foundry's other customers.
"We have not seen the yield challenges that other early adopters have seen with 40nm," Greenfield insisted. "It hasn't been perfect but it has gone very well in terms of yield. The methodology that we have working with TSMC has served us very well.
"At 28nm, we already have several test chips. We have done four test chips and have a fifth taping out and will probably have a sixth and seventh before taping out a product," said Greenfield.