At the company’s executive forum held in Yokohama, Japan, TSMC’s senior vice president of R&D, Shang-yi Chiang, provided some background on why yield problems surfaced on the 40nm process — and also some indications that 28nm will not exactly be plain sailing.
Chiang pointed to the shift to immersion lithography — a choice that Intel delayed by a generation — and the use of a new low-k dielectric in the metal layers as the main culprits for the foundry’s problems. He claimed that defect density has reduced significantly since the middle of last year, when chairman Morris Chang decided to expand the team working on 40nm at TSMC.
Chiang said the move from 90nm to 65nm was comparatively simple and the relative cost quite low. “Moving to 45 and 40nm is a lot more challenging,” he said. “This is the first time we began to use 193nm immersion [lithography]. This means the photoresist during exposure is submerged in water and [presents] a very high potential defect [density].”
The low-k dielectric, with a dielectric constant 2.5, was also more fragile than its predecessor. It seems that 40nm was a partial rerun of the 130nm introduction when chipmakers discovered that soft dielectrics and packaging machinery are not the best of mates — the pressure needed to seal the package crushed the metal interconnect.
As Altera fared much better than nVidia in getting yielding silicon from 40nm, it suggests that the biggest problem lay in wirebond packages. High-end FPGAs tend to use flip-chip packaging. It’s more expensive to use, which is why you don’t want to use it if possible on high-volume devices, but the controlled collapse the process uses presumably develops a lot less stress than the punch from a gold wirebonder.
An FPGA also has greater opportunities for redundancy in the interconnect, although not too much as these devices are interconnect-limited. Chiang pointed to graphics processors in particular as challenging as they have a couple of billion vias on them. “You can imagine the degree of challenge when you try to make every one of these two billion vias functional,” said Chiang.
In practice, however, companies such as nVidia do implement redundant vias where possible as the disappearing via problem has been with the industry since the introduction of 130nm.
Chiang added: “So, moving to 40nm, that’s why it’s getting pretty challenging, pretty difficult to do. And going forward to 28nm, the biggest difficulty by far is the high-k metal gate. It’s really [going to introduce] a lot of material issues.”
Chiang said the company is “only four months away from mass production of 28LP”, which is the version of 28nm that uses a conventional polysilicon gate. This process is mainly for low-speed, high-density devices, such as baseband and application processors in mobile phones. He said the yield on 64Mbit SRAM test chips around 65 per cent. “This is a quite comfortable number at this stage of the technology and we don’t see much [of a] problem at this moment.”
The bigger change comes towards the end of the year, at least, with the introduction of the higher-speed metal-gate process. “We are not as ready as 28LP. For example, the yield is only 26 per cent, instead of 65 per cent, but we have three more months to go. Actually, we have five months from now and I believe we can catch up with the yield. And 28HPL will be introduced at the end of this year. At this time, we achieve a 15 per cent yield for 64Mbit,” Chiang claimed.
“For all those three versions we are feeling quite comfortable compared to our past experience at this stage of the development,” he added.
Like Intel, TSMC has found that the traditional laggard in the transistor-speed stakes, the p-channel device, is coming out faster than expected. This is partly because it’s currently relatively easy to apply strain to the p-channel using buried layers of silicon germanium.
Chiang said the performance of the n-channel transistors on 28nm is, right now, about 5 per cent behind the target that was determined by modelling in SPICE. “For the PMOS, we are about 5 per cent better than target at the moment,” he said.
Because of the issues with the reliability of very low-k dielectrics, Chiang said the company is shifting attention from trying to reduce capacitance in the metal interconnect — which is determined partly by the dielectric constant of the insulator — to improving resistance of the metal lines themselves. It’s not entirely clear from Chiang’s presentation whether this is an across-the-board move or simply the use of wider metal lines for high-speed circuits.
Also like Intel, TSMC is making the design rules for 28nm more restrictive. These will help reduce variability. Having the polysilicon used to form the gate run in just one direction, it’s possible to make the edge of the gate smoother. The company will also disallow the jogs, short gates and T-shapes often used in dense standard cells to save space (as shown in the diagram above). Line-edge roughness is now a major contributor to variability. Chiang said C/D control is easier with polysilicon running in just one direction. It’s something that Intel used to great effect in its recent processor designs.
Chiang claimed the introduction of restricted design rules has nothing to do with the decision, like Intel and in contrast to the Common Platform group, to adopt a gate-last approach to making a high-k metal gate.
“There are misunderstandings that TSMC introduced RDR mainly because of the gate-last [structure]. I’d like to share with you the reason we use RDR had little to do with the choice of gate-last. The [reason] is more for the performance and for the control which will result in [better] yield and cost.”
There is a penalty to introducing this kind of restriction: gate density plummets. Chiang said a 70 per cent linear shrink generally leads to a two-fold improvement in areal density from process generation to generation. Factor in the restricted design rules, and the areal improvement is just 1.6x. “So there’s a 40 per cent layout penalty and that’s very, very significant. However, this can be recovered if we adopt a different layout style, and it’s not difficult to do,” Chiang claimed.
It’s not clear what this style looks like and how it affects standard-cell design in particular. But Chiang added: “TSMC has demonstrated that it will be very willing to share with our customers on how we did that and I’m sure there is more than one way to do that.”
A question is whether TSMC will share that information equally with independent library developers. ARM has been keen to stress how close its relationship is to IBM and the Common Platform partners with its 32nm and 28nm library development programme. There is little doubt that TSMC will share information with the likes of Altera and nVidia. Will that also go for ARM’s Artisan group or, indeed, AMD and Xilinx which have stronger links with the Common Platform group of foundries?