TSMC explains 40nm yield problems, metal-gate stacks and why 100 per cent utilisation is bad


With Morris Chang back in the CEO seat, it was a different kind of Taiwan Semiconductor (TSMC) that you could hear on the second quarter 2009 results conference call today. Analyst questions actually got some answers for a change, not least a hint as to which way TSMC plans to go with the high-k, metal-gate process for the future 28nm node.

The company will be taking the same route as Intel and UMC with a so-called gate-last process, not the gate-first approach favoured by IBM and the Common Platform partners. However, that answer from senior director of advanced process technologies Mark Liu did not arrive without a little prodding from his boss. It's hard to imagine former CEO - and now man in charge of finding new markets at TSMC - Rick Tsai making sure Liu answered the question.

Liu's answer to Daiwa Securities' Pranab Sharm about what was different to the Common Platform plan actually started out as: "We think our technology is competitive with IBM's tech but most importantly the 32nm customers are already engaged and designs are already ongong. On 28nm high-k metalgate we have ten customers already engaged. We expect that for customer engagments we are on the same track...the right track."

Chang cut in: "I think he is asking..."

We then found out: "Yes we have a different architecture in terms of gate-first and gate-last..."

Sharma had another go: "Are you going to use both or one? Are you going to use the gate-first or gate-last?"

"We will be using gate-last," admitted Liu.

Liu was there not so much to talk about the 32nm and 28nm processes which look to have slipped by about a quarter in terms of when they get underway, but the problems with yield that are rumoured to have tripped up nVidia.

Liu started off by claiming that the average yield has roughly doubled within the past three months since the primary causes of failure emerged. In the previous conference call in April, Tsai confessed that the foundry had problems with 40nm but claimed that the root cause of the problem had been found.

Liu cited two materials changes, including the use of silicon germanium to strain the silicon layers, and a move to immersion lithography contributed to problems with defects, as being responsible for being a tougher step than the shift to 65nm, which only involved a change in lithography. “We encountered major issues,” he said.

Liu explained the major problem with yield lay in the stress layers produced by adding different amounts of silicon germanium.

Several senior R&D directors – two experts on process modules and one on integration – were drafted in to work on the problem during the past quarter. Morris Chang, the chairman who has stepped in as CEO since Q1, added later that R&D spend has been increased to put more effort into work on advanced processes. “If we had not increased our R&D resources, that kind of help would have been very difficult to come by,” Chang claimed.

Previously, TSMC has been running with a long-term R&D spend of around 6-7 per cent of revenue. This has gone up to 7.8 per cent, said Chang, admitting that the actual spend was not that big because of the drop in 2009 revenues but insisted that between 7 per cent and 8 per cent would be the long-term average. He does not want the 28nm ramp-up to provide the company with another banana skin to slip on and it marks one of the differences in TSMC's approach since Chang took over as CEO.

"It would be incorrect to say that I have new strategies. Even as chairman I had a hand in the strategy of the company. What is new is that I now have the opportunity and first-hand responsibility to push my thinking and my strategy vigourously," said Chang.

The shift in R&D spending is one sign of that. Another is a long-term plan that sounds slightly strange in the context of the foundry business: to not run at maximum capacity. For close to 18 months ahead of the current recession, TSMC was operating at close to 100 per cent utilisation or even higher (you can do that by dedicating a little less time to maintenance). This very high utilisation proved a turn-off to the bigger customers who went and looked for secondary suppliers, just in case TSMC turned round one day and said: "No more wafers for a while."

So, the plan is to have TSMC operate at 95 per cent utilisation or less, once things return to normal, so as not to scare too many customers into seeking dual-source arrangements. This, Chang claimed, will help maintain per-wafer pricing at levels TSMC wants.

On the 40nm process, Liu said the foundry is attempting to ramp-up yield through the summer. “We have several activities in place to move the yield forward. We expect the defect density reduction will continue through September.”

Chang admitted that the yield problems reduced the profitability of the 40nm process. “The profitability is not nearly as good as that on 65nm or the other nodes. But we do expect that when the yields improve along the experience curve that we have seen for every other node in the past then I think 40nm profitability will be going up to the standard that we expect.”