The Toyota plan for chips


In the latest issue of IEEE Spectrum, Professor Clayton Christensen (of The Innovator's Dilemma fame) and colleagues describe their role in trying to improve efficiency at a big chipmaker, taking much of their inspiration from the Toyota Production System. The company goes unnamed, but I assume that it's not Intel as some of what they describe was put into action at the number-one chipmaker in its Copy Exact programme.

One thing that the authors note - and one that strikes just about anybody who visits a fab - is how much manual intervention chipmaking processes need. They are more automated than they used to be. Intel was able to turn two fabs into one at Leixlip in Ireland thanks to a monorail for wafers that runs between corridors of equipment. It was not long ago that boxes of wafers travelled on trolleys pushed by people.

There were good reasons for not automating heavily. It was easier to train people to deal with small changes and a given piece of equipment can take hours to process a full box of wafers. Why go to the bother of automating when people can react in plenty of time?

But, as Christensen and colleagues write, having a lot of on-the-spot manual changes makes it difficult to trace problems back to their source. By having the processes formalised and recorded, and then working on ways to improve them, the authors claim they were able to reduce wafer processing costs by 12 per cent and cycle time - perhaps more important in an environment where being able to respond to sudden changes in demand has become critical - by 67 per cent.

Details will differ, but the project conducted by Christensen and colleagues sounds very similar in concept to the Next Generation Fab proposals coming from the Japanese fab owners and from work at Sematech. In the past, operational efficiencies came from Moore's Law and from increases in wafer size. But the incremental costs are now so high that it makes sense to look more at the minutiae of operating fabs. It is perhaps a further symptom of the way in which Moore's Law is pricing itself out of the mainstream.

The piece ends on a slightly bizarre note - one so optimistic you start to wonder whether the authors have been anywhere near chip design. They argue that, for manufacturers to make the most of the efficiencies in applying the Toyota system to their operations, they need to remake the design process. The answer is to make things modular. Yes, slap that forehead hard. If only we realised that was the answer!

This is the point at which Christensen and colleagues need to do an analysis of what costs money in design. Little things like embedded software. It's true that chipmakers could do more to standardise and cut costs but the idea of plug-and-play components that let you slap together a system like a Dell PC is only workable in certain environments. And, few of those environments demand full-custom chips - microcontrollers and field-programmable gate arrays (FPGAs) will often do just fine.