May 2009 Archives

Amid the bizarre theories surrounding a sale of Twitter to Apple, it's easy to forget that some acquisitions do actually make sense. A couple of deals have shown two of the bigger EDA companies sealing good-value deals. Yesterday it was Mentor Graphics buying Logicvision, the design-for-test (DFT) company that Virage Logic coveted. Today, Synopsys stepped in to pluck MIPS Technologies' analogue IP unit for a fraction of what MIPS had paid for Chipidea, the company that formed the backbone of the unit.

In both cases, the heads of Mentor and Synopsys should be pretty happy. If the MIPS deal looked inexpensive at $22m, consider the $13m Mentor agreed to for Logicvision in a field that is much more central to its focus that Synopsys' on IP.

Virage chief scientist Yervant Zorian has favoured putting yield-monitoring IP cores into working chips for some time. I remember him giving a tutorial at DAC some years back on how on-chip instrumentation could work and guide the yield-ramp process. Having a test company with experience in hooking up chips to the outside world would have been useful - and Zorian was chief technical advisor to Logicvision. But it was not to be, for Virage at least.

The deal for Logicvision is pretty small but it fits a longer-term project to extend Mentor's reach in test and design-for-manufacture (DFM). Mentor is not quite as far ahead of Synopsys in test as it is with Calibre but the company has made a series of moves that bolster its position as the company with all the cards in the difficult interface between chip design and the fab. It's the same space that Cadence Design Systems desperately wanted, but only to come away with a bloody nose.

The Synopsys deal is a bit more prosaic but it's one that a lot of sense for the EDA company. It has arguably the widest portfolio of IP cores on the market and more in the analogue space can't hurt. And it has a services arm that can absorb the design-consultancy work - given that custom design work was a substantial part of Chipidea's business when MIPS bought it, it seems reasonable that Synopsys should keep this on.

The problem for MIPS was that it just didn't have the breadth of customers to push the analogue cores out to a lot of people. Arguably that was the point of the deal: make MIPS less dependent on its processors in an environment where ARM seems to be at every turn. For MIPS, the deal provides it some money having blown most of its cash on the original purchase of Chipidea. But the long-term picture for MIPS is not all that great.

MIPS' former base was the high-performance embedded processor. But with ARM, Intel and nVidia encroaching on this space from different angles, it's hard to see where MIPS can go. Unless you are already invested in the architecture, it's hard to see why people would buy into it unless it was provided at a significant discount to an ARM licence. And that doesn't do MIPS that much good as IP support doesn't come cheap. To be fair, up to the Chipidea purchase, MIPS' sales were improving but it remains to be seen whether the processor company can repeat that growth or whether the analogue purchase knocked it too far off course.

These two deal this week means that a much bigger deal - the widely expected sale of Magma Design Automation - is likely to miss the week of the sensible deals. What could that mean?

In his keynote at the recent Design Automation and Test in Europe conference, ARM CTO Mike Muller spent a little bit of time to say thank-you for some of the electronic design automation (EDA) tools out there. One perhaps unexpected beneficiary - because it usually gets no respect - was design for test (DFT).

Indeed, when DFT engineer John Ford spotted how Mentor Graphics' Joe Sawicki referred to the technique as being instrumental to the future of chipmaking on Twitter, John Blyler of Chip Design magazine, and probably others, thought it a little strange. As the man who has headed up Mentor's design for manufacturing (DFM) strategy for more than ten years, surely Sawicki meant that, and not DFT?

For Muller, DFT or test automation makes it possible to test chips. "We couldn't have hand-stitched all those scan chains," he said. But lots of EDA is about automation. The other aspect of DFT that has emerged in the past few years is its role in yield prediction and planning, and Muller very briefly alluded to this use for DFT. As yield more or less equals profit (assuming you're not in dumping territory), it is easy to believe that DFT has a crucial role in chipmaking.

I'd link to an interview I did with Mentor's chief scientist and test expert Janusz Rajski several years ago, but it has effectively disappeared offline. So, the rest of this post is that interview. I have done a more recent interview with him but but it hasn't been published as yet, so I'll do a follow-up with changes. Hopefully, this should go some way to explaining why some people in the chip-design business suddenly love DFT. This is the pre-edit copy, so there might be some typos in it - I just took one out.