At first glance, the 40nm process presented by Toshiba at IEDM last week looks no great shakes. In a session dominated by 32nm processes, this one seemed not just one generation behind but a bit more than that if you compared its headline figures with the 45nm technologies described by Intel and TSMC in 2007. But a closer inspection reveals a process with a bit more going for it.
When Toshiba says it's a 40nm, the company means the gate measures 40nm. This is a good 30 per cent longer than the minimum gate length quoted by Intel and TSMC last year and puts the transistor more in line with a 65nm or 55nm process – actual gate length has outpaced the notional length contained in each node's title for some years. As a result, figures such as current drive, which control the performance of the core transistors, are lower than those quoted by TSMC. The NMOS transistor of Toshiba's high-speed version of the process has a current drive of 840µA/µm, around 30 per cent worse than the process that turned into TSMC's own shot at a 40nm technology.
But, if you compare with a 65nm process, where transistors often wind up in the 40nm-long range, Toshiba's numbers are par for the course. The bulk technology covered by IBM and the Common Platform partners at IEDM in 2004 shows broadly similar numbers. More importantly, the leakage in the new Toshiba process is lower than in those older processes thanks to the decision to implant nitrogen atoms in the transistor channel, the use of flash-lamp annealing and just a touch of high-k in the gate over the channel, without going all the way to high-k, metal-gate structures.
Among other things, these techniques cut band-to-band tunnelling, one big source of leakage in low-power transistors according to Toshiba. By putting hafnium into an otherwise conventional silicon oxynitride gate dielectric, the gate gets slightly better control over the transistor channel, improving drive current by up to 5 per cent. Toshiba takes this boost to reduce the concentration of dopant atoms in the channel. Why? They are big source of variability in deep submicron devices because you can now count the number of active dopants in a channel in the hundreds. It will not be long before you count them in tens.
The lower dopant concentration cuts the junction leakage and the variability. This gave the Toshiba engineers the confidence to scale the SRAM cell down to just 0.195µm2, a little smaller than TSMC's 0.202µm2 cell supported on its 40/45nm process. With lower variability, there is less chance of individual cells failing, which helps keep yield high.
The contacted gate pitch for logic is also reasonably competitive with the other 40/45nm processes from the likes of IBM, Intel and TSMC, although a bit looser at 168nm versus TSMC's 162nm.
This is a process that is designed for density and low power consumption not performance and marks the continuing separation between semiconductor processes as feature sizes scale down. Toshiba is not alone in doing this kind of optimisation – favouring gate density over gate length – Panasonic (formerly Matsushita) has been doing the same thing. In consumer electronics, where these processes are aimed, cost is still king. That means optimising for overall die area ahead of optimising for performance. As a result, Panasonic uses longer, more conservative transistor designs.
At the Chipworks meeting after close of play on Tuesday (16 December), senior technical analyst Dick James showed pictures of recent Panasonic processes to underline his point. "Panasonic is an interesting company," said James. "They bring out processes that are leading edge in terms of their [market] timing but they have far less stress and strain engineering than the competition uses. The density all comes from packing the gates closer together."