When I last interviewed Wilf Corrigan, before he moved up to chairman and ultimately parted company with LSI Logic, he argued that the Japanese chipmakers made one crucial mistake in the 1990s. They didn't trust chemical mechanical polishing (CMP).
I have a lot of sympathy for the Japanese technologists. If someone came to you and said: "We know you've taken a lot of care to put down those transistors. They're incredibly delicate structures. That's why we think you should go at the wafer with a Brillo pad and a bucket of acid."
In essence, CMP is a high-tech scouring process. You lower an abrasive pad onto a spinning wafer and you add a chemical slurry and you keep going until you think the wafer has been polished flat. Believe it or not, this works. CMP flattens surfaces other techniques cannot reach. Before CMP, the top surfaces of chips were lumpy affairs. Each layer you put down made it lumpier. It meant there was a limit to how much wiring you could get on the chip. Three layers and you were about done. A section through a chip looked more like a geological diagram of what rock strata look like after a few earthquakes.
The industry could not stick with three layers, they had to go higher. But they had to deal with the lumpiness. The answer was to take the scouring pad to the wafer after putting down another layer of metal. Believing that they could not control the quality of the polishing, the Japanese held back. But the US companies pressed on and started to retake a lead in chipmaking they lost ten years previously.
Intel reckons CMP can do a lot more. And Joseph Steigerwald turned up to IEDM in San Francisco to let them know what. There is an Intel-oriented subtext to his paean to the high-tech Brillo pad: it's a key component of the process used to make the metal gate stacks in the company's 45nm process and, most likely, the 32nm version. Where the rest of the business is focusing on the gate-first approach, Intel reckons that its approach works better. And CMP makes it possible.
The other place where CMP is going to be crucial is going to be in 3D integration, particularly where chips are bonded together and connected using metal vias that extend all the way through the wafer. And this is where another surprisingly reliable technology, reactive ion etch, plays a big role. Etching is arguably one of the most precise tools available to process engineers even though it revolves around pumping noxious gases into a chamber where they can start eating into the silicon. Luckily, those gases don't eat away at the hard masks that seal off portions of the wafer.
For things that look as though they really shouldn't work, CMP and etching have done pretty well for themselves.