Just ahead of Apple’s launch of the iPhone 4, Carmelo Papa, general manager of STMicroelectronics’ industrial and multisegment sector, was bullish about a new market for the company. He declared that this year would be the dawn of the ‘era of the gyroscope’.

A few days later, Apple CEO Steve Jobs was demonstrating what the combination of an accelerometer and three-axis gyroscope could do in a mobile handset. ST made its own video for the company’s Field Trip, a series of presentations to financial analysts, to show how the gyro and accelerometer combination could be used to navigate through the streets of Venice - using dead reckoning where the signals from GPS satellites cannot be easily seen in narrow streets.

As ST is the only vendor claiming to make an integrated three-axis gyroscope, this is the one that is suspected to be inside the iPhone 4. Teardown experts such as Chipworks and TechInsights believe die markings confirm ST as the manufacturer.

Benedetto Vigna, head of ST’s MEMS division, claimed that the market for gyros in consumer will be three times bigger than that for similar sensors in automotive – where they are more widely used today for stabilisation control – by 2014.

Although the initial demonstrations revolve around games, Vigna said dead-reckoning calculations can make it possible to pinpoint a user’s location inside buildings such as shops and museums, narrowing location-based information to a rack of clothes or a museum exhibit.

Although it does not need all three axes, optical image stabilisation is another use for cameras and phones. Papa said applications for the MEMS gyro can go further, including vibration control in washing machines. “The potential market is huge,” he said.

According to Benedetto Vigna, the decision to make a three-axis gyro was taken quite late in the day in an indication of how integration and fast turnaround are becoming crucial in getting MEMS into high-volume consumer designs. “By the end of last year, we understood that the market was willing to move faster,” said, explaining that the company had been working on a two-axis design.

“On the 21st October, we put the first transistors on the layout. And you are now holding the product,” he said as he handed out tiny 4x4mm packages. “Because of the nimbleness of the team we now have a three-axis gyroscope.”

After going through an acquisition spree of its own, Virage Logic has agreed to be bought by EDA company Synopsys for about $315m in cash. The move follows only a month after Cadence Design Systems’ announcement of its plan to buy memory-IP specialist Denali.

The rationale from Aart de Geus, CEO of Synopsys, in the conference call for the purchase is not all that different from Cadence’s. “Putting together these IP blocks and making sure they work together is essential,” he said.

Like Cadence, Synopsys is expecting an increase in the use of third-party IP by chipmakers. “The trend of IP outsourcing is a massive trend. People are moving towards using commercial IP where they can except where they can add differentiation,” de Geus said, adding that a growing number of companies are realising what they thought was differentiated home-grown IP could be just a millstone. “What companies produce is not necessarily differentiated. Some of the standards they need to work with are so complex, their own people can’t necessarily do a cost-efficient job there. The downturn has helped many executives realise that outsourcing these efforts makes a lot of sense.”

De Geus argued that very little of the IP produced by Virage overlaps with that created at Synopsys. The EDA company backed away from the acquisition of memory-IP specialist Mosys in 2004 and has not developed its own. Even earlier, a move into standard-cell IP through the acquisition of Silicon Architects in the mid-1990s ended when Synopsys wound up the operation. De Geus explained that the move was “premature” and that it had gone into the business before it had a place-and-route tool (later acquired through its 2002 purchase of Avant) that would make use of those cells.

Virage’s roots lie in low-level IP such as memory cores and standard cells but has, more recently, moved into larger cores through the acquisition of ARC International and NXP Semiconductors’ IP design group. Potentially, the addition of the Virage line-up brings Synopsys into conflict with ARM, with which Synopsys developed the verification reuse and low-power design methodologies.

De Geus argued that the processors from ARC complement those of ARM, agreeing with one analyst’s use of the term ‘ancillary’ to describe them. “ARM is one of our most important partners and is a friend of the company, a company around which we have built a number of our offerings. ARC is interesting because it so supports the ARM core processor. It provides a controller that can be used for subtasks to offload the main processor. It will be interesting to see how we can build solutions with ARM.”

ARM has gradually backed away from areas that Synopsys has moved into in the IP space. The ARM Primexsys portfolio of peripherals failed to take off but Synopsys’s main successes in IP lie in this area. Although ARM has tried to get into digital signal processing (DSP), it is another area that the UK company has discontinued its effort, choosing to focus on graphics instead. ARC has, in contrast, focused heavily on audio and similar DSP-based products.

Where ARM and Synopsys will compete head-on is in standard-cell libraries and it’s a business where ARM has spent heavily to keep up with process technology. Having Virage provides Synopsys with a way to align design-implementation tools with the cell libraries, something that is becoming more important as design rules get ever more restrictive. Will ARM engineers get the same access to the Synopsys tools people post-acquisition?

Belgium-based research institute IMEC has teamed up with Intel and a group of local universities on a programme that is intended to pave the way for exascale computers – supercomputers that are close to a thousand times more powerful than those being commissioned today.

“In 1997, we saw the first terascale machines. A few years ago, petascale appeared. We will hit exascale in around 2018,” said Wilfried Verachtert, high-performance computing project manager at IMEC, explaining that these machines will be able to perform 1018 floating-point calculations per second.

The most powerful supercomputer being made today is the Cray XT5 Jaguar with a rated performance of close to 2 petaflops

At a presentation held to celebrate the opening of a new cleanroom at IMEC and the foundation of the ExaScience lab, Martin Curley, senior principal engineer and director of Intel Labs Europe, said: “We are focused on creating the future of supercomputing. We have a job to do of creating a sustainable future. Exascale computing can really change our world.”

Curley said a the two main problems will be power consumption and the difficulty of writing highly parallel software. The performance required is the equivalent of 50 million laptops which would demand thousands of megawatts of power.

He explained that, by the time exascale computers are likely to appear, silicon-chip geometries will have dropped to 10nm. Although these devices can potentially run at tens of gigahertz, Curley said power consumption concerns would force supercomputer makers to run them much more slowly and potentially even slower than today’s processors. The move will demand billions of processing units in one supercomputer. “How are we going to achieve that? The only way is through billion-operation parallelism.”

Curley added: “Even with just 10 to 12 cores, we see the performance of commercial microprocessors begin to degrade. The biggest single challenge is parallelism.”

The ExaScience lab will, as its test application, work on software to predict the damage caused by the powerful magnetic fields that follow solar flares in the hope of providing more accurate information to satellite operators and the power-grid companies.

With current-generation supercomputers, the mesh used to analyse field strength has elements that are a million kilometres across, far larger than the Earth itself. An exascale machine would make it possible to scale the mesh size down to elements that are 10,000km across.

Verachtert said the project aims to get the power consumption of a machine from 7000MW – based on today’s technology - to 50MW, “and that is still higher than we want”.

One problem with a supercomputer than contains millions of discrete processors, each one containing thousands of processing elements, is the expected failure rate. “My optimistic projection is that there will be a failure every minute. It’s possible that there will be a failure every second. We have to do something about that.”

The failure rate will have a knock-on effect on programming. Today, it is possible to break up applications so that portions can be re-run after a hardware failure, which may happen once a day. That is impossible as the size of the machine scales up. Verachtert said the methods programmers use will have to take account of processors failing, using checkpoints and other techniques such as transactional memory – which Intel has researched heavily already – to allow code to be re-run automatically without disrupting other parts of the application.

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